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Terje Bergstrom 945e5e6832 gpu: nvgpu: gp10b: Correct SMMU bit number 
Bit 36 is the correct bit to indicate SMMU translation.

Bug 1580756

Change-Id: I761e70265d5981b07940f1d43716416829993827
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/658827
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
2016-12-27 15:22:03 +05:30
..
nvgpu
gpu: nvgpu: gp10b: Correct SMMU bit number
2016-12-27 15:22:03 +05:30