Alex Frid 9635e19e61 gpu: nvgpu: Don't increase GPCPLL rate before bypass ...

Do not force GM20b GPCPLL post divider to 1:2 settings before switching
to bypass clock if PLL output frequency is increased as a result. Move
this step under bypass. However, this step is still needed in case when
PLL can be configured without switch to bypass.

Bug 1450787

Change-Id: Iab81b0e5a71f44f738a64e15b05df41fdbd61ebe
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/456505
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

2015-03-18 12:11:01 -07:00

..

nvgpu

gpu: nvgpu: Don't increase GPCPLL rate before bypass

2015-03-18 12:11:01 -07:00