Vinod G 96d4842c0d gpu: nvgpu: gv11b: fix PMA list alignment in ctxsw buffer ...

ucode changed so that it expects LIST_nv_perf_pma_ctx_reg
list in ctxsw buffer to be 256 byte aligned. This change
was added to gv100 before, adding similar change to gv11b.

bug 2045640

Change-Id: I1f92d38e607f70d5602ef6d5c607b9dc20807245
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747895
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2018-07-12 20:43:55 -07:00

..

nvgpu

gpu: nvgpu: gv11b: fix PMA list alignment in ctxsw buffer

2018-07-12 20:43:55 -07:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00