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d0907087c1
gfxp_wfi_timeout_count/unit fields were stored in gr_gk20a.ctx_vars struct so that any user could configure them through sysfs nodes But the sysfs nodes are legacy and not being actively used by anyone. Hence delete the sysfs nodes to configure these fields. Since the gfxp timeout unit/count can now be statically programmed, make following changes - remove g->ops.gr.init_gfxp_wfi_timeout_count() hal - remove g->ops.gr.get_max_gfxp_wfi_timeout_count() hal - update g->ops.gr.init.preemption_state() hals to configure the values using macros instead of caller passing the values - update g->ops.gr.init.gfxp_wfi_timeout() hals to configure the values using macros instead of caller passing the values Finally, we don't need to store gfxp_wfi_timeout_count/unit fields anymore, hence delete them from gr_gk20a.ctx_vars Jira NVGPU-3112 Change-Id: Idbe5ab3053228dd177aca253545aac36d38ca8ad Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2100219 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
92 lines
3.8 KiB
C
92 lines
3.8 KiB
C
/*
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* GP10B GPU GR
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_GP10B_H
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#define NVGPU_GR_GP10B_H
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#include "gk20a/mm_gk20a.h"
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struct gk20a;
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struct nvgpu_gr_isr_data;
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struct nvgpu_gr_ctx;
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struct nvgpu_preemption_modes_rec;
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struct gk20a_debug_output;
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#define NVC097_SET_GO_IDLE_TIMEOUT 0x022cU
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU
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#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028U
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#define NVC097_SET_RD_COALESCE 0x102cU
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280U
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528U
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#define NVC097_SET_BES_CROP_DEBUG3 0x10c4U
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#define NVC097_SET_BES_CROP_DEBUG4 0x10b0U
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528U
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#define NVC0C0_SET_RD_COALESCE 0x0228U
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#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0U
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#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1U
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void gr_gp10b_create_sysfs(struct gk20a *g);
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void gr_gp10b_remove_sysfs(struct gk20a *g);
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int gr_gp10b_handle_fecs_error(struct gk20a *g,
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struct channel_gk20a *__ch,
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struct nvgpu_gr_isr_data *isr_data);
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int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
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struct channel_gk20a *fault_ch);
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int gr_gp10b_handle_sm_exception(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm,
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bool *post_event, struct channel_gk20a *fault_ch,
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u32 *hww_global_esr);
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int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, bool patch);
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void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data);
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void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data);
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int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data);
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void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
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void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data);
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int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
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struct gk20a_debug_output *o);
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void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
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int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
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bool sm_debugger_attached, struct channel_gk20a *fault_ch,
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bool *early_exit, bool *ignore_debugger);
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u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
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u32 gpc, u32 tpc, u32 sm);
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u32 get_ecc_override_val(struct gk20a *g);
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int gr_gp10b_suspend_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
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bool boost);
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int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
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struct nvgpu_preemption_modes_rec *preemption_modes_rec);
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int gp10b_gr_fuse_override(struct gk20a *g);
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int gr_gp10b_init_preemption_state(struct gk20a *g);
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bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
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bool *cilp_preempt_pending);
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#endif /* NVGPU_GR_GP10B_H */
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