Vedashree Vidwans 9aae6bcf4d gpu: nvgpu: fix MISRA violations hal.fifo.pbdma ...

Rule 10.x necessitates operands to have essential type; and left and
right operands should be of same width and type.
This patch fixes rule 10.x errors in nvgpu/hal/fifo/pbdma_gp10b.c

Jira NVGPU-3822

Change-Id: I4f0b49b784695cdbd8d4e1dc67c8c7d1f78b08bf
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2154336
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-07-22 11:55:01 -07:00

..

nvgpu

gpu: nvgpu: fix MISRA violations hal.fifo.pbdma

2019-07-22 11:55:01 -07:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00