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git://nv-tegra.nvidia.com/linux-nvgpu.git
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3885fe099a
Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder to support cross platform feature implementation. Made changes to files which accessed include pmuif/* to reflect pmuif/* movement changes. Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files. Jira NVGPU-19 Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1299823 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
128 lines
3.4 KiB
C
128 lines
3.4 KiB
C
/*
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* general power channel structures & definitions
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*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _PWRPOLICY_H_
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#define _PWRPOLICY_H_
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include "boardobj/boardobjgrp.h"
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#include "boardobj/boardobj.h"
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#include "ctrl/ctrlpmgr.h"
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#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4
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enum pwr_policy_limit_id {
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PWR_POLICY_LIMIT_ID_MIN = 0x00000000,
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PWR_POLICY_LIMIT_ID_RATED,
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PWR_POLICY_LIMIT_ID_MAX,
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PWR_POLICY_LIMIT_ID_CURR,
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PWR_POLICY_LIMIT_ID_BATT,
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};
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struct pwr_policy {
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struct boardobj super;
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u8 ch_idx;
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u8 num_limit_inputs;
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u8 limit_unit;
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s32 limit_delta;
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u32 limit_min;
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u32 limit_rated;
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u32 limit_max;
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u32 limit_batt;
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struct ctrl_pmgr_pwr_policy_info_integral integral;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_min;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_rated;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_max;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_batt;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_curr;
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u8 sample_mult;
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enum ctrl_pmgr_pwr_policy_filter_type filter_type;
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union ctrl_pmgr_pwr_policy_filter_param filter_param;
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};
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struct pwr_policy_ext_limit {
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u8 policy_table_idx;
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u32 limit;
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};
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struct pwr_policy_batt_workitem {
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u32 power_state;
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bool b_full_deflection;
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};
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struct pwr_policy_client_workitem {
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u32 limit;
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bool b_pending;
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};
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struct pwr_policy_relationship {
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struct boardobj super;
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u8 policy_idx;
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};
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struct pmgr_pwr_policy {
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u8 version;
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bool b_enabled;
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struct nv_pmu_perf_domain_group_limits global_ceiling;
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u8 policy_idxs[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES];
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struct pwr_policy_ext_limit ext_limits[PWR_POLICY_EXT_POWER_STATE_ID_COUNT];
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s32 ext_power_state;
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u16 base_sample_period;
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u16 min_client_sample_period;
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u8 low_sampling_mult;
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struct boardobjgrp_e32 pwr_policies;
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struct boardobjgrp_e32 pwr_policy_rels;
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struct boardobjgrp_e32 pwr_violations;
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struct pwr_policy_client_workitem client_work_item;
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};
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struct pwr_policy_limit {
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struct pwr_policy super;
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};
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struct pwr_policy_hw_threshold {
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struct pwr_policy_limit super;
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u8 threshold_idx;
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u8 low_threshold_idx;
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bool b_use_low_threshold;
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u16 low_threshold_value;
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};
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struct pwr_policy_sw_threshold {
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struct pwr_policy_limit super;
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u8 threshold_idx;
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u8 low_threshold_idx;
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bool b_use_low_threshold;
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u16 low_threshold_value;
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u8 event_id;
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};
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union pwr_policy_data_union {
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struct boardobj boardobj;
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struct pwr_policy pwrpolicy;
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struct pwr_policy_hw_threshold hw_threshold;
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struct pwr_policy_sw_threshold sw_threshold;
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} ;
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#define PMGR_GET_PWR_POLICY(g, policy_idx) \
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((struct pwr_policy *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super), (policy_idx)))
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#define PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy) \
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((ppolicy)->num_limit_inputs++)
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u32 pmgr_policy_sw_setup(struct gk20a *g);
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#endif
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