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9dd2a8fc73
The memory bandwidth reported by the nvgpu driver is a resultant of FBP and EMC floorsweeping status. The FBP floorsweep status was already getting reported in the GPU characterstics so the status of EMC was fetched and reported in this change. Jira NVGPU-9609 Bug 3661074 Change-Id: Ia2fe6cb029d086765da15d9e964ea77256e06604 Signed-off-by: atanand <atanand@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859237 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
59 lines
2.7 KiB
C
59 lines
2.7 KiB
C
/*
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* GA10B FUSE
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*
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* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FUSE_GA10B_H
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#define NVGPU_FUSE_GA10B_H
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#define GA10B_FUSE_READ_DEVICE_IDENTIFIER_RETRIES 100000U
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struct gk20a;
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struct nvgpu_fuse_feature_override_ecc;
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int ga10b_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
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bool ga10b_fuse_is_opt_ecc_enable(struct gk20a *g);
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bool ga10b_fuse_is_opt_feature_override_disable(struct gk20a *g);
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u32 ga10b_fuse_status_opt_gpc(struct gk20a *g);
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u32 ga10b_fuse_status_opt_fbio(struct gk20a *g);
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u32 ga10b_fuse_status_opt_fbp(struct gk20a *g);
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u32 ga10b_fuse_status_opt_l2_fbp(struct gk20a *g, u32 fbp);
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u32 ga10b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
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void ga10b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
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u32 ga10b_fuse_opt_priv_sec_en(struct gk20a *g);
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u32 ga10b_fuse_opt_sm_ttu_en(struct gk20a *g);
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void ga10b_fuse_write_feature_override_ecc(struct gk20a *g, u32 val);
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void ga10b_fuse_write_feature_override_ecc_1(struct gk20a *g, u32 val);
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void ga10b_fuse_read_feature_override_ecc(struct gk20a *g,
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struct nvgpu_fuse_feature_override_ecc *ecc_feature);
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int ga10b_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi);
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u32 ga10b_fuse_opt_sec_debug_en(struct gk20a *g);
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u32 ga10b_fuse_status_opt_emc(struct gk20a *g);
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u32 ga10b_fuse_opt_secure_source_isolation_en(struct gk20a *g);
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int ga10b_fuse_check_priv_security(struct gk20a *g);
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int ga10b_fetch_falcon_fuse_settings(struct gk20a *g, u32 falcon_id,
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unsigned long *fuse_settings);
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u32 ga10b_fuse_status_opt_pes_gpc(struct gk20a *g, u32 gpc);
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u32 ga10b_fuse_status_opt_rop_gpc(struct gk20a *g, u32 gpc);
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#endif /* NVGPU_FUSE_GA10B_H */
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