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The power rail of dGPU is managed with help of a set of GPIOs. Using those GPIOs add an interface to power off and power on dGPU. Before dGPU is powered off, new work is blocked by setting NVGPU_DRIVER_IS_DYING and current jobs are allowed to finish by waiting for gpu to be idle. The tegra PCIe controller driver provided APIs tegra_pcie_attach_controller() and tegra_pcie_detach_controller() are used to manage PCIe link shutdown, PCIe refclk management and PCIe rescan. JIRA NVGPU-1100 Change-Id: Ifae5b81535f40dceca5292a987d3daf6984f3210 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1749847 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
37 lines
1.4 KiB
C
37 lines
1.4 KiB
C
/*
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* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __NVGPU_COMMON_LINUX_MODULE_H__
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#define __NVGPU_COMMON_LINUX_MODULE_H__
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struct gk20a;
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struct device;
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struct nvgpu_os_linux;
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int gk20a_pm_finalize_poweron(struct device *dev);
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int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l);
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void gk20a_remove_support(struct gk20a *g);
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void gk20a_driver_start_unload(struct gk20a *g);
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int nvgpu_quiesce(struct gk20a *g);
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int nvgpu_remove(struct device *dev, struct class *class);
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int nvgpu_start_gpu_idle(struct gk20a *g);
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int nvgpu_wait_for_gpu_idle(struct gk20a *g);
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void nvgpu_free_irq(struct gk20a *g);
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struct device_node *nvgpu_get_node(struct gk20a *g);
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void __iomem *nvgpu_devm_ioremap_resource(struct platform_device *dev, int i,
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struct resource **out);
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void __iomem *nvgpu_devm_ioremap(struct device *dev, resource_size_t offset,
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resource_size_t size);
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extern struct class nvgpu_class;
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#endif
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