mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 01:02:34 +03:00
255 lines
7.0 KiB
C
255 lines
7.0 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/firmware.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/acr.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/soc.h>
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#include "acr_bootstrap.h"
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#include "acr_priv.h"
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int nvgpu_acr_wait_for_completion(struct gk20a *g, struct hs_acr *acr_desc,
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u32 timeout)
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{
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u32 flcn_id;
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#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
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u32 sctl, cpuctl;
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#endif
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int completion = 0;
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u32 data = 0;
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u32 bar0_status = 0;
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u32 error_type;
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nvgpu_log_fn(g, " ");
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flcn_id = nvgpu_falcon_get_id(acr_desc->acr_flcn);
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completion = nvgpu_falcon_wait_for_halt(acr_desc->acr_flcn, timeout);
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if (completion != 0) {
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nvgpu_err(g, "flcn-%d: HS ucode boot timed out, limit: %d ms",
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flcn_id, timeout);
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error_type = ACR_BOOT_TIMEDOUT;
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goto exit;
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}
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if (acr_desc->acr_engine_bus_err_status != NULL) {
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completion = acr_desc->acr_engine_bus_err_status(g,
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&bar0_status, &error_type);
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if (completion != 0) {
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nvgpu_err(g, "flcn-%d: ACR engine bus error", flcn_id);
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goto exit;
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}
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}
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data = nvgpu_falcon_mailbox_read(acr_desc->acr_flcn, FALCON_MAILBOX_0);
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if (data != 0U) {
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nvgpu_err(g, "flcn-%d: HS ucode boot failed, err %x", flcn_id,
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data);
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nvgpu_err(g, "flcn-%d: Mailbox-1 : 0x%x", flcn_id,
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nvgpu_falcon_mailbox_read(acr_desc->acr_flcn,
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FALCON_MAILBOX_1));
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completion = -EAGAIN;
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error_type = ACR_BOOT_FAILED;
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goto exit;
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}
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/*
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* When engine-falcon is used for ACR bootstrap, validate the integrity
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* of falcon IMEM and DMEM.
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*/
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if (acr_desc->acr_validate_mem_integrity != NULL) {
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if (!acr_desc->acr_validate_mem_integrity(g)) {
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nvgpu_err(g, "flcn-%d: memcheck failed", flcn_id);
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completion = -EAGAIN;
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error_type = ACR_BOOT_FAILED;
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}
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}
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exit:
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#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
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nvgpu_falcon_get_ctls(acr_desc->acr_flcn, &sctl, &cpuctl);
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nvgpu_acr_dbg(g, "flcn-%d: sctl reg %x cpuctl reg %x",
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flcn_id, sctl, cpuctl);
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#endif
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if (completion != 0) {
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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nvgpu_falcon_dump_stats(acr_desc->acr_flcn);
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#endif
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if (acr_desc->report_acr_engine_bus_err_status != NULL) {
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acr_desc->report_acr_engine_bus_err_status(g,
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bar0_status, error_type);
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}
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}
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return completion;
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}
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/*
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* Patch signatures into ucode image
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*/
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static void acr_ucode_patch_sig(struct gk20a *g,
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unsigned int *p_img, unsigned int *p_prod_sig,
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unsigned int *p_dbg_sig, unsigned int *p_patch_loc,
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unsigned int *p_patch_ind, u32 sig_size)
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{
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#if defined(CONFIG_NVGPU_NEXT)
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struct nvgpu_acr *acr = g->acr;
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#endif
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unsigned int i, j, *p_sig;
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const u32 dmem_word_size = 4U;
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nvgpu_acr_dbg(g, " ");
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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p_sig = p_prod_sig;
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nvgpu_acr_dbg(g, "PRODUCTION MODE\n");
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} else {
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p_sig = p_dbg_sig;
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nvgpu_info(g, "DEBUG MODE\n");
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}
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#if defined(CONFIG_NVGPU_NEXT)
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if (acr->get_versioned_sig != NULL) {
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p_sig = acr->get_versioned_sig(g, acr, p_sig, &sig_size);
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}
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#endif
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/* Patching logic:*/
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sig_size = sig_size / dmem_word_size;
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for (i = 0U; i < (sizeof(*p_patch_loc) / dmem_word_size); i++) {
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for (j = 0U; j < sig_size; j++) {
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p_img[nvgpu_safe_add_u32(
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(p_patch_loc[i] / dmem_word_size), j)] =
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p_sig[nvgpu_safe_add_u32(
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(p_patch_ind[i] * dmem_word_size), j)];
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}
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}
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}
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/*
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* Loads ACR bin to SYSMEM/FB and bootstraps ACR with bootloader code
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* start and end are addresses of ucode blob in non-WPR region
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*/
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int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc)
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{
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struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
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struct bin_hdr *hs_bin_hdr = NULL;
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struct acr_fw_header *fw_hdr = NULL;
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u32 *ucode_header = NULL;
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u32 *ucode = NULL;
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u32 timeout = 0;
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int err = 0;
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nvgpu_acr_dbg(g, "ACR TYPE %x ", acr_desc->acr_type);
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if (acr_fw != NULL) {
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err = acr->patch_wpr_info_to_ucode(g, acr, acr_desc, true);
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if (err != 0) {
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nvgpu_err(g, "Falcon ucode patch wpr info failed");
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return err;
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}
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} else {
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/* Firmware is stored in soc specific path in FMODEL
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* Hence NVGPU_REQUEST_FIRMWARE_NO_WARN is used instead
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* of NVGPU_REQUEST_FIRMWARE_NO_SOC
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*/
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#ifdef CONFIG_NVGPU_SIM
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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acr_fw = nvgpu_request_firmware(g,
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acr_desc->acr_fw_name,
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NVGPU_REQUEST_FIRMWARE_NO_WARN);
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} else
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#endif
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{
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acr_fw = nvgpu_request_firmware(g,
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acr_desc->acr_fw_name,
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NVGPU_REQUEST_FIRMWARE_NO_SOC);
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}
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if (acr_fw == NULL) {
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nvgpu_err(g, "%s ucode get fail for %s",
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acr_desc->acr_fw_name, g->name);
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return -ENOENT;
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}
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acr_desc->acr_fw = acr_fw;
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err = acr->patch_wpr_info_to_ucode(g, acr, acr_desc, false);
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if (err != 0) {
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nvgpu_err(g, "Falcon ucode patch wpr info failed");
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goto err_free_ucode;
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}
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}
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hs_bin_hdr = (struct bin_hdr *)(void *)acr_fw->data;
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fw_hdr = (struct acr_fw_header *)(void *)(acr_fw->data +
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hs_bin_hdr->header_offset);
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ucode_header = (u32 *)(void *)(acr_fw->data + fw_hdr->hdr_offset);
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ucode = (u32 *)(void *)(acr_fw->data + hs_bin_hdr->data_offset);
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/* Patch Ucode signatures */
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acr_ucode_patch_sig(g, ucode,
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(u32 *)(void *)(acr_fw->data + fw_hdr->sig_prod_offset),
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(u32 *)(void *)(acr_fw->data + fw_hdr->sig_dbg_offset),
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(u32 *)(void *)(acr_fw->data + fw_hdr->patch_loc),
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(u32 *)(void *)(acr_fw->data + fw_hdr->patch_sig),
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fw_hdr->sig_dbg_size);
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err = nvgpu_falcon_hs_ucode_load_bootstrap(acr_desc->acr_flcn,
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ucode, ucode_header);
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if (err != 0) {
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nvgpu_err(g, "HS ucode load & bootstrap failed");
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goto err_free_ucode;
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}
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/* wait for complete & halt */
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if (nvgpu_platform_is_silicon(g)) {
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timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS;
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} else {
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timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS;
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}
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err = nvgpu_acr_wait_for_completion(g, acr_desc, timeout);
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if (err != 0) {
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nvgpu_err(g, "HS ucode completion err %d", err);
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goto err_free_ucode;
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}
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return 0;
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err_free_ucode:
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nvgpu_release_firmware(g, acr_fw);
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acr_desc->acr_fw = NULL;
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return err;
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}
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