mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 01:02:34 +03:00
286 lines
8.2 KiB
C
286 lines
8.2 KiB
C
/*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr_sw_tu104.h"
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#include <nvgpu/gk20a.h>
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#include <nvgpu/firmware.h>
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#include "acr_wpr.h"
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#include "acr_priv.h"
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#include "acr_blob_alloc.h"
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#include "acr_bootstrap.h"
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#include "acr_blob_construct.h"
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#include "acr_sw_gv11b.h"
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#include "acr_sw_tu104.h"
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static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr)
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{
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int err = 0;
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nvgpu_log_fn(g, " ");
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err = nvgpu_acr_bootstrap_hs_ucode(g, g->acr, &g->acr->acr_ahesasc);
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if (err != 0) {
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nvgpu_err(g, "ACR AHESASC bootstrap failed");
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goto exit;
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}
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err = nvgpu_acr_bootstrap_hs_ucode(g, g->acr, &g->acr->acr_asb);
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if (err != 0) {
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nvgpu_err(g, "ACR ASB bootstrap failed");
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goto exit;
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}
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exit:
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return err;
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}
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/* WPR info update */
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static int tu104_acr_patch_wpr_info_to_ucode(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc,
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bool is_recovery)
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{
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struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
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struct acr_fw_header *acr_fw_hdr = NULL;
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struct bin_hdr *acr_fw_bin_hdr = NULL;
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struct flcn_acr_desc *acr_dmem_desc;
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struct wpr_carveout_info wpr_inf;
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u32 *acr_ucode_header = NULL;
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u32 *acr_ucode_data = NULL;
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u64 tmp_addr;
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nvgpu_log_fn(g, " ");
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acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
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acr_fw_hdr = (struct acr_fw_header *)
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(acr_fw->data + acr_fw_bin_hdr->header_offset);
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acr_ucode_data = (u32 *)(acr_fw->data + acr_fw_bin_hdr->data_offset);
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acr_ucode_header = (u32 *)(acr_fw->data + acr_fw_hdr->hdr_offset);
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acr->get_wpr_info(g, &wpr_inf);
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acr_dmem_desc = (struct flcn_acr_desc *)
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&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
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acr_dmem_desc->nonwpr_ucode_blob_start = wpr_inf.nonwpr_base;
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nvgpu_assert(wpr_inf.size <= U32_MAX);
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acr_dmem_desc->nonwpr_ucode_blob_size = (u32)wpr_inf.size;
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acr_dmem_desc->regions.no_regions = 1U;
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acr_dmem_desc->wpr_offset = 0U;
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acr_dmem_desc->wpr_region_id = 1U;
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acr_dmem_desc->regions.region_props[0U].region_id = 1U;
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tmp_addr = (wpr_inf.wpr_base) >> 8U;
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nvgpu_assert(u64_hi32(tmp_addr) == 0U);
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acr_dmem_desc->regions.region_props[0U].start_addr = U32(tmp_addr);
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tmp_addr = ((wpr_inf.wpr_base) + wpr_inf.size) >> 8U;
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nvgpu_assert(u64_hi32(tmp_addr) == 0U);
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acr_dmem_desc->regions.region_props[0U].end_addr = U32(tmp_addr);
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tmp_addr = wpr_inf.nonwpr_base >> 8U;
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nvgpu_assert(u64_hi32(tmp_addr) == 0U);
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acr_dmem_desc->regions.region_props[0U].shadowmMem_startaddress =
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U32(tmp_addr);
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return 0;
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}
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/* LSF init */
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static u32 tu104_acr_lsf_sec2(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* SEC2 LS falcon info */
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lsf->falcon_id = FALCON_ID_SEC2;
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lsf->falcon_dma_idx = NV_SEC2_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = false;
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lsf->is_priv_load = false;
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lsf->get_lsf_ucode_details = nvgpu_acr_lsf_sec2_ucode_details;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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static u32 tu104_acr_lsf_pmu(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* PMU support not required until PSTATE support is enabled */
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if (!g->support_ls_pmu) {
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/* skip adding LS PMU ucode to ACR blob */
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return 0;
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}
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/* PMU LS falcon info */
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lsf->falcon_id = FALCON_ID_PMU;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = false;
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lsf->is_priv_load = false;
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#ifdef CONFIG_NVGPU_LS_PMU
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lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details;
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lsf->get_cmd_line_args_offset = nvgpu_pmu_fw_get_cmd_line_args_offset;
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#endif
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return BIT32(lsf->falcon_id);
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}
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static u32 tu104_acr_lsf_fecs(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* FECS LS falcon info */
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lsf->falcon_id = FALCON_ID_FECS;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = true;
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lsf->is_priv_load = true;
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lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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static u32 tu104_acr_lsf_gpccs(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* FECS LS falcon info */
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lsf->falcon_id = FALCON_ID_GPCCS;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = true;
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lsf->is_priv_load = true;
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lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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static u32 tu104_acr_lsf_conifg(struct gk20a *g,
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struct nvgpu_acr *acr)
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{
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u32 lsf_enable_mask = 0;
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lsf_enable_mask |= tu104_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]);
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lsf_enable_mask |= tu104_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]);
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lsf_enable_mask |= tu104_acr_lsf_gpccs(g, &acr->lsf[FALCON_ID_GPCCS]);
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lsf_enable_mask |= tu104_acr_lsf_sec2(g, &acr->lsf[FALCON_ID_SEC2]);
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return lsf_enable_mask;
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}
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/* fusa signing enable check */
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static bool tu104_acr_is_fusa_enabled(struct gk20a *g)
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{
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return g->is_fusa_sku;
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}
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/* ACR-AHESASC(ACR hub encryption setter and signature checker) init*/
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static void tu104_acr_ahesasc_v0_ucode_select(struct gk20a *g,
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struct hs_acr *acr_ahesasc)
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{
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acr_ahesasc->acr_type = ACR_AHESASC_NON_FUSA;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_NON_FUSA_PROD_UCODE;
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} else {
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acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_NON_FUSA_DBG_UCODE;
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}
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}
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static void tu104_acr_ahesasc_fusa_ucode_select(struct gk20a *g,
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struct hs_acr *acr_ahesasc)
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{
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acr_ahesasc->acr_type = ACR_AHESASC_FUSA;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_FUSA_PROD_UCODE;
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} else {
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acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_FUSA_DBG_UCODE;
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}
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}
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static void tu104_acr_ahesasc_sw_init(struct gk20a *g,
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struct hs_acr *acr_ahesasc)
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{
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if (tu104_acr_is_fusa_enabled(g)) {
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tu104_acr_ahesasc_fusa_ucode_select(g, acr_ahesasc);
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} else {
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tu104_acr_ahesasc_v0_ucode_select(g, acr_ahesasc);
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}
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acr_ahesasc->acr_flcn = &g->sec2.flcn;
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}
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/* ACR-ASB(ACR SEC2 booter) init*/
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static void tu104_acr_asb_v0_ucode_select(struct gk20a *g,
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struct hs_acr *acr_asb)
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{
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acr_asb->acr_type = ACR_ASB_NON_FUSA;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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acr_asb->acr_fw_name = HSBIN_ACR_ASB_NON_FUSA_PROD_UCODE;
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} else {
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acr_asb->acr_fw_name = HSBIN_ACR_ASB_NON_FUSA_DBG_UCODE;
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}
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}
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static void tu104_acr_asb_fusa_ucode_select(struct gk20a *g,
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struct hs_acr *acr_asb)
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{
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acr_asb->acr_type = ACR_ASB_FUSA;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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acr_asb->acr_fw_name = HSBIN_ACR_ASB_FUSA_PROD_UCODE;
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} else {
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acr_asb->acr_fw_name = HSBIN_ACR_ASB_FUSA_DBG_UCODE;
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}
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}
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static void tu104_acr_asb_sw_init(struct gk20a *g,
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struct hs_acr *acr_asb)
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{
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if (tu104_acr_is_fusa_enabled(g)) {
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tu104_acr_asb_fusa_ucode_select(g, acr_asb);
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} else {
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tu104_acr_asb_v0_ucode_select(g, acr_asb);
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}
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acr_asb->acr_flcn = &g->gsp_flcn;
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}
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void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
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{
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nvgpu_log_fn(g, " ");
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acr->lsf_enable_mask = tu104_acr_lsf_conifg(g, acr);
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acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob;
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acr->get_wpr_info = nvgpu_acr_wpr_info_vid;
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acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_vid;
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acr->bootstrap_owner = FALCON_ID_GSPLITE;
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acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
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acr->patch_wpr_info_to_ucode = tu104_acr_patch_wpr_info_to_ucode;
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/* Init ACR-AHESASC */
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tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
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/* Init ACR-ASB*/
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tu104_acr_asb_sw_init(g, &acr->acr_asb);
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}
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