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git://nv-tegra.nvidia.com/linux-nvgpu.git
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90 lines
3.1 KiB
C
90 lines
3.1 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_ZBC_PRIV_H
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#define NVGPU_GR_ZBC_PRIV_H
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#include <nvgpu/gr/zbc.h>
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/* Opaque black (i.e. solid black, fmt 0x28 = A8B8G8R8) */
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#define GR_ZBC_SOLID_BLACK_COLOR_FMT 0x28
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/* Transparent black = (fmt 1 = zero) */
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#define GR_ZBC_TRANSPARENT_BLACK_COLOR_FMT 0x1
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/* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */
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#define GR_ZBC_SOLID_WHITE_COLOR_FMT 0x2
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/* z format with fp32 */
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#define GR_ZBC_Z_FMT_VAL_FP32 0x1
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#define GR_ZBC_STENCIL_CLEAR_FMT_INVAILD 0U
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#define GR_ZBC_STENCIL_CLEAR_FMT_U8 1U
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struct zbc_color_table {
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u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 format;
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u32 ref_cnt;
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};
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struct zbc_depth_table {
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u32 depth;
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u32 format;
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u32 ref_cnt;
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};
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struct zbc_stencil_table {
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u32 stencil;
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u32 format;
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u32 ref_cnt;
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};
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struct nvgpu_gr_zbc_entry {
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u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 depth;
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u32 stencil;
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u32 type;
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u32 format;
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};
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/*
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* HW ZBC table valid entries start at index 1.
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* Entry 0 is reserved to mean "no matching entry found, do not use ZBC"
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*/
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struct nvgpu_gr_zbc {
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struct nvgpu_mutex zbc_lock; /* Lock to access zbc table */
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struct zbc_color_table *zbc_col_tbl; /* SW zbc color table pointer */
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struct zbc_depth_table *zbc_dep_tbl; /* SW zbc depth table pointer */
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struct zbc_stencil_table *zbc_s_tbl; /* SW zbc stencil table pointer */
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u32 min_color_index; /* Minimum valid color table index */
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u32 min_depth_index; /* Minimum valid depth table index */
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u32 min_stencil_index; /* Minimum valid stencil table index */
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u32 max_color_index; /* Maximum valid color table index */
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u32 max_depth_index; /* Maximum valid depth table index */
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u32 max_stencil_index; /* Maximum valid stencil table index */
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u32 max_used_color_index; /* Max used color table index */
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u32 max_used_depth_index; /* Max used depth table index */
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u32 max_used_stencil_index; /* Max used stencil table index */
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};
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#endif /* NVGPU_GR_ZBC_PRIV_H */
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