mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
133 lines
3.8 KiB
C
133 lines
3.8 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/firmware.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/sbr.h>
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#include "sbr.h"
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static void pub_ucode_patch_sig(struct gk20a *g,
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unsigned int *p_img, unsigned int *p_prod_sig,
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unsigned int *p_dbg_sig, unsigned int *p_patch_loc,
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unsigned int *p_patch_ind, u32 sig_size)
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{
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unsigned int i, j, *p_sig;
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nvgpu_info(g, " ");
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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p_sig = p_prod_sig;
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nvgpu_info(g, "PRODUCTION MODE\n");
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} else {
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p_sig = p_dbg_sig;
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nvgpu_info(g, "DEBUG MODE\n");
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}
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/* Patching logic:*/
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sig_size = sig_size / 4U;
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for (i = 0U; i < (sizeof(*p_patch_loc)>>2U); i++) {
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for (j = 0U; j < sig_size; j++) {
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p_img[nvgpu_safe_add_u32((p_patch_loc[i]>>2U), j)] =
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p_sig[nvgpu_safe_add_u32((p_patch_ind[i]<<2U), j)];
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}
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}
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}
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int nvgpu_sbr_pub_load_and_execute(struct gk20a *g)
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{
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struct nvgpu_firmware *pub_fw = NULL;
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struct pub_bin_hdr *hs_bin_hdr = NULL;
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struct pub_fw_header *fw_hdr = NULL;
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u32 *ucode_header = NULL;
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u32 *ucode = NULL;
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u32 data = 0;
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int err = 0;
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nvgpu_log_fn(g, " ");
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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pub_fw = nvgpu_request_firmware(g, PUB_PROD_BIN,
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NVGPU_REQUEST_FIRMWARE_NO_SOC);
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} else {
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pub_fw = nvgpu_request_firmware(g, PUB_DBG_BIN,
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NVGPU_REQUEST_FIRMWARE_NO_SOC);
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}
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if (pub_fw == NULL) {
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nvgpu_err(g, "pub ucode get fail");
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err = -ENOENT;
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goto exit;
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}
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hs_bin_hdr = (struct pub_bin_hdr *)(void *)pub_fw->data;
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fw_hdr = (struct pub_fw_header *)(void *)(pub_fw->data +
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hs_bin_hdr->header_offset);
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ucode_header = (u32 *)(void *)(pub_fw->data +
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fw_hdr->hdr_offset);
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ucode = (u32 *)(void *)(pub_fw->data + hs_bin_hdr->data_offset);
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/* Patch Ucode signatures */
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pub_ucode_patch_sig(g, ucode,
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(u32 *)(void *)(pub_fw->data + fw_hdr->sig_prod_offset),
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(u32 *)(void *)(pub_fw->data + fw_hdr->sig_dbg_offset),
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(u32 *)(void *)(pub_fw->data + fw_hdr->patch_loc),
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(u32 *)(void *)(pub_fw->data + fw_hdr->patch_sig),
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fw_hdr->sig_dbg_size);
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err = nvgpu_falcon_hs_ucode_load_bootstrap(&g->sec2.flcn, ucode,
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ucode_header);
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if (err != 0) {
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nvgpu_err(g, "pub ucode load & bootstrap failed");
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goto exit;
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}
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if (nvgpu_falcon_wait_for_halt(&g->sec2.flcn, PUB_TIMEOUT) != 0) {
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nvgpu_err(g, "pub ucode boot timed out");
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err = -ETIMEDOUT;
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goto exit;
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}
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data = nvgpu_falcon_mailbox_read(&g->sec2.flcn, FALCON_MAILBOX_0);
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if (data != 0U) {
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nvgpu_err(g, "pub ucode boot failed, err %x", data);
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err = -EAGAIN;
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goto exit;
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}
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exit:
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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if (err != 0) {
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nvgpu_falcon_dump_stats(&g->sec2.flcn);
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}
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#endif
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if (pub_fw != NULL) {
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nvgpu_release_firmware(g, pub_fw);
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}
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nvgpu_log_fn(g, "pub loaded & executed with status %d", err);
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return err;
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}
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