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git://nv-tegra.nvidia.com/linux-nvgpu.git
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51 lines
1.6 KiB
C
51 lines
1.6 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_COMMON_SBR_H_
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#define NVGPU_COMMON_SBR_H_
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#define PUB_PROD_BIN "pub.bin"
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#define PUB_DBG_BIN "pub_dbg.bin"
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#define PUB_TIMEOUT 100U /* msec */
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struct pub_bin_hdr {
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u32 bin_magic;
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u32 bin_ver;
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u32 bin_size;
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u32 header_offset;
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u32 data_offset;
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u32 data_size;
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};
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struct pub_fw_header {
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u32 sig_dbg_offset;
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u32 sig_dbg_size;
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u32 sig_prod_offset;
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u32 sig_prod_size;
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u32 patch_loc;
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u32 patch_sig;
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u32 hdr_offset;
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u32 hdr_size;
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};
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#endif /* NVGPU_COMMON_SBR_H_ */
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