mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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94 lines
3.1 KiB
C
94 lines
3.1 KiB
C
/*
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* GM20B Graphics
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GM20B_CLK_GM20B_H
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#define NVGPU_GM20B_CLK_GM20B_H
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#include <nvgpu/lock.h>
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struct gk20a;
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struct clk_gk20a;
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struct nvgpu_clk_pll_debug_data {
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u32 trim_sys_sel_vco_reg;
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u32 trim_sys_sel_vco_val;
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u32 trim_sys_gpc2clk_out_reg;
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u32 trim_sys_gpc2clk_out_val;
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u32 trim_sys_bypassctrl_reg;
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u32 trim_sys_bypassctrl_val;
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u32 trim_sys_gpcpll_cfg_reg;
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u32 trim_sys_gpcpll_dvfs2_reg;
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u32 trim_bcast_gpcpll_dvfs2_reg;
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u32 trim_sys_gpcpll_cfg_val;
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bool trim_sys_gpcpll_cfg_enabled;
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bool trim_sys_gpcpll_cfg_locked;
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bool trim_sys_gpcpll_cfg_sync_on;
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u32 trim_sys_gpcpll_coeff_val;
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u32 trim_sys_gpcpll_coeff_mdiv;
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u32 trim_sys_gpcpll_coeff_ndiv;
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u32 trim_sys_gpcpll_coeff_pldiv;
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u32 trim_sys_gpcpll_dvfs0_val;
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u32 trim_sys_gpcpll_dvfs0_dfs_coeff;
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u32 trim_sys_gpcpll_dvfs0_dfs_det_max;
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u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset;
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};
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int gm20b_init_clk_setup_sw(struct gk20a *g);
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int gm20b_clk_prepare(struct clk_gk20a *clk);
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void gm20b_clk_unprepare(struct clk_gk20a *clk);
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int gm20b_clk_is_prepared(struct clk_gk20a *clk);
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unsigned long gm20b_recalc_rate(struct clk_gk20a *clk, unsigned long parent_rate);
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int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate,
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unsigned long parent_rate);
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long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate,
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unsigned long *parent_rate);
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struct pll_parms *gm20b_get_gpc_pll_parms(void);
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int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val);
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int gm20b_init_clk_support(struct gk20a *g);
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void gm20b_suspend_clk_support(struct gk20a *g);
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int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val);
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int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val);
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int gm20b_clk_get_pll_debug_data(struct gk20a *g,
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struct nvgpu_clk_pll_debug_data *d);
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/* 1:1 match between post divider settings and divisor value */
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static inline u32 nvgpu_pl_to_div(u32 pl)
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{
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return pl;
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}
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static inline u32 nvgpu_div_to_pl(u32 divisor)
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{
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return divisor;
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}
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#endif /* NVGPU_GM20B_CLK_GM20B_H */
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