mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
133 lines
3.7 KiB
C
133 lines
3.7 KiB
C
/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/string.h>
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#include "falcon_gk20a.h"
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#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
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bool gk20a_falcon_clear_halt_interrupt_status(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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u32 base_addr = flcn->flcn_base;
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u32 data = 0;
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bool status = false;
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gk20a_writel(g, base_addr + falcon_falcon_irqsclr_r(),
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gk20a_readl(g, base_addr + falcon_falcon_irqsclr_r()) |
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0x10U);
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data = gk20a_readl(g, (base_addr + falcon_falcon_irqstat_r()));
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if ((data & falcon_falcon_irqstat_halt_true_f()) !=
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falcon_falcon_irqstat_halt_true_f()) {
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/*halt irq is clear*/
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status = true;
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}
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return status;
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}
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int gk20a_falcon_copy_from_dmem(struct nvgpu_falcon *flcn,
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u32 src, u8 *dst, u32 size, u8 port)
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{
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struct gk20a *g = flcn->g;
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u32 base_addr = flcn->flcn_base;
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u32 i, words, bytes;
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u32 data, addr_mask;
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u32 *dst_u32 = (u32 *)dst;
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nvgpu_log_fn(g, " src dmem offset - %x, size - %x", src, size);
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words = size >> 2U;
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bytes = size & 0x3U;
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addr_mask = falcon_falcon_dmemc_offs_m() |
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g->ops.falcon.dmemc_blk_mask();
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src &= addr_mask;
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nvgpu_writel(g, base_addr + falcon_falcon_dmemc_r(port),
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src | falcon_falcon_dmemc_aincr_f(1));
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for (i = 0; i < words; i++) {
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dst_u32[i] = nvgpu_readl(g,
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base_addr + falcon_falcon_dmemd_r(port));
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}
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if (bytes > 0U) {
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data = nvgpu_readl(g, base_addr + falcon_falcon_dmemd_r(port));
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nvgpu_memcpy(&dst[words << 2U], (u8 *)&data, bytes);
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}
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return 0;
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}
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int gk20a_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src,
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u8 *dst, u32 size, u8 port)
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{
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struct gk20a *g = flcn->g;
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u32 base_addr = flcn->flcn_base;
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u32 *dst_u32 = (u32 *)dst;
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u32 words = 0;
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u32 bytes = 0;
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u32 data = 0;
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u32 blk = 0;
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u32 i = 0;
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nvgpu_log_info(g, "download %d bytes from 0x%x", size, src);
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words = size >> 2U;
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bytes = size & 0x3U;
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blk = src >> 8;
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nvgpu_log_info(g, "download %d words from 0x%x block %d",
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words, src, blk);
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nvgpu_writel(g, base_addr + falcon_falcon_imemc_r(port),
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falcon_falcon_imemc_offs_f(src >> 2) |
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g->ops.falcon.imemc_blk_field(blk) |
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falcon_falcon_dmemc_aincr_f(1));
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for (i = 0; i < words; i++) {
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dst_u32[i] = nvgpu_readl(g,
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base_addr + falcon_falcon_imemd_r(port));
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}
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if (bytes > 0U) {
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data = nvgpu_readl(g, base_addr + falcon_falcon_imemd_r(port));
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nvgpu_memcpy(&dst[words << 2U], (u8 *)&data, bytes);
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}
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return 0;
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}
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void gk20a_falcon_get_ctls(struct nvgpu_falcon *flcn, u32 *sctl,
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u32 *cpuctl)
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{
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*sctl = gk20a_readl(flcn->g, flcn->flcn_base + falcon_falcon_sctl_r());
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*cpuctl = gk20a_readl(flcn->g, flcn->flcn_base +
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falcon_falcon_cpuctl_r());
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}
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