mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
223 lines
6.9 KiB
C
223 lines
6.9 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/log2.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/io.h>
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#include <nvgpu/bitops.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/debug.h>
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#include <nvgpu/error_notifier.h>
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#include <nvgpu/nvhost.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/ptimer.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pbdma_status.h>
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#include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h>
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#include "pbdma_gm20b.h"
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#define PBDMA_SUBDEVICE_ID 1U
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void gm20b_pbdma_intr_enable(struct gk20a *g, bool enable)
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{
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u32 pbdma_id = 0;
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u32 intr_stall;
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u32 num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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if (!enable) {
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gm20b_pbdma_disable_and_clear_all_intr(g);
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return;
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}
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/* clear and enable pbdma interrupts */
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for (pbdma_id = 0; pbdma_id < num_pbdma; pbdma_id++) {
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gm20b_pbdma_clear_all_intr(g, pbdma_id);
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intr_stall = nvgpu_readl(g, pbdma_intr_stall_r(pbdma_id));
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intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f();
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nvgpu_writel(g, pbdma_intr_stall_r(pbdma_id), intr_stall);
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nvgpu_log_info(g, "pbdma id:%u, intr_en_0 0x%08x", pbdma_id,
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intr_stall);
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nvgpu_writel(g, pbdma_intr_en_0_r(pbdma_id), intr_stall);
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intr_stall = nvgpu_readl(g, pbdma_intr_stall_1_r(pbdma_id));
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/*
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* For bug 2082123
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* Mask the unused HCE_RE_ILLEGAL_OP bit from the interrupt.
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*/
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intr_stall &= ~pbdma_intr_stall_1_hce_illegal_op_enabled_f();
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nvgpu_log_info(g, "pbdma id:%u, intr_en_1 0x%08x", pbdma_id,
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intr_stall);
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nvgpu_writel(g, pbdma_intr_en_1_r(pbdma_id), intr_stall);
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}
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}
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bool gm20b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
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u32 *error_notifier)
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{
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bool recover = true;
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/*
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* all of the interrupts in _intr_1 are "host copy engine"
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* related, which is not supported. For now just make them
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* channel fatal.
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*/
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nvgpu_err(g, "hce err: pbdma_intr_1(%d):0x%08x",
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pbdma_id, pbdma_intr_1);
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return recover;
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}
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u32 gm20b_pbdma_get_signature(struct gk20a *g)
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{
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return pbdma_signature_hw_valid_f() | pbdma_signature_sw_zero_f();
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}
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u32 gm20b_pbdma_channel_fatal_0_intr_descs(void)
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{
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/*
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* These are data parsing, framing errors or others which can be
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* recovered from with intervention... or just resetting the
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* channel
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*/
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u32 channel_fatal_0_intr_descs =
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pbdma_intr_0_gpfifo_pending_f() |
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pbdma_intr_0_gpptr_pending_f() |
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pbdma_intr_0_gpentry_pending_f() |
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pbdma_intr_0_gpcrc_pending_f() |
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pbdma_intr_0_pbptr_pending_f() |
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pbdma_intr_0_pbentry_pending_f() |
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pbdma_intr_0_pbcrc_pending_f() |
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pbdma_intr_0_method_pending_f() |
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pbdma_intr_0_methodcrc_pending_f() |
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pbdma_intr_0_pbseg_pending_f() |
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pbdma_intr_0_signature_pending_f();
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return channel_fatal_0_intr_descs;
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}
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void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
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struct nvgpu_debug_context *o,
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struct nvgpu_channel_dump_info *info)
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{
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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u32 syncpointa, syncpointb;
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syncpointa = info->inst.syncpointa;
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syncpointb = info->inst.syncpointb;
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if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v())
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&& (pbdma_syncpointb_wait_switch_v(syncpointb) ==
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pbdma_syncpointb_wait_switch_en_v())) {
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gk20a_debug_output(o, "%s on syncpt %u (%s) val %u",
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info->hw_state.pending_acquire ? "Waiting" : "Waited",
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pbdma_syncpointb_syncpt_index_v(syncpointb),
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nvgpu_nvhost_syncpt_get_name(g->nvhost,
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(int) pbdma_syncpointb_syncpt_index_v(syncpointb)),
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pbdma_syncpointa_payload_v(syncpointa));
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}
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#endif
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}
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void gm20b_pbdma_setup_hw(struct gk20a *g)
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{
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u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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u32 i, timeout;
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for (i = 0U; i < host_num_pbdma; i++) {
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timeout = nvgpu_readl(g, pbdma_timeout_r(i));
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timeout = set_field(timeout, pbdma_timeout_period_m(),
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pbdma_timeout_period_max_f());
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nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", timeout);
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nvgpu_writel(g, pbdma_timeout_r(i), timeout);
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}
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}
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u32 gm20b_pbdma_get_fc_formats(void)
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{
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return (pbdma_formats_gp_fermi0_f() | pbdma_formats_pb_fermi1_f() |
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pbdma_formats_mp_fermi0_f());
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}
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u32 gm20b_pbdma_get_fc_pb_header(void)
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{
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return (pbdma_pb_header_priv_user_f() |
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pbdma_pb_header_method_zero_f() |
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pbdma_pb_header_subchannel_zero_f() |
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pbdma_pb_header_level_main_f() |
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pbdma_pb_header_first_true_f() |
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pbdma_pb_header_type_inc_f());
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}
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void gm20b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o)
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{
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u32 i, host_num_pbdma;
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struct nvgpu_pbdma_status_info pbdma_status;
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host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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gk20a_debug_output(o, "PBDMA Status - chip %-5s", g->name);
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gk20a_debug_output(o, "-------------------------");
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for (i = 0; i < host_num_pbdma; i++) {
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g->ops.pbdma_status.read_pbdma_status_info(g, i,
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&pbdma_status);
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gk20a_debug_output(o, "pbdma %d:", i);
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gk20a_debug_output(o,
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" id: %d - %-9s next_id: - %d %-9s | status: %s",
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pbdma_status.id,
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nvgpu_pbdma_status_is_id_type_tsg(&pbdma_status) ?
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"[tsg]" : "[channel]",
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pbdma_status.next_id,
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nvgpu_pbdma_status_is_next_id_type_tsg(
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&pbdma_status) ?
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"[tsg]" : "[channel]",
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nvgpu_fifo_decode_pbdma_ch_eng_status(
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pbdma_status.pbdma_channel_status));
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gk20a_debug_output(o,
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" PBDMA_PUT %016llx PBDMA_GET %016llx",
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(u64)nvgpu_readl(g, pbdma_put_r(i)) +
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((u64)nvgpu_readl(g, pbdma_put_hi_r(i)) << 32ULL),
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(u64)nvgpu_readl(g, pbdma_get_r(i)) +
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((u64)nvgpu_readl(g, pbdma_get_hi_r(i)) << 32ULL));
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gk20a_debug_output(o,
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" GP_PUT %08x GP_GET %08x "
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"FETCH %08x HEADER %08x",
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nvgpu_readl(g, pbdma_gp_put_r(i)),
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nvgpu_readl(g, pbdma_gp_get_r(i)),
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nvgpu_readl(g, pbdma_gp_fetch_r(i)),
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nvgpu_readl(g, pbdma_pb_header_r(i)));
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gk20a_debug_output(o,
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" HDR %08x SHADOW0 %08x SHADOW1 %08x",
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nvgpu_readl(g, pbdma_hdr_shadow_r(i)),
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nvgpu_readl(g, pbdma_gp_shadow_0_r(i)),
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nvgpu_readl(g, pbdma_gp_shadow_1_r(i)));
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}
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gk20a_debug_output(o, " ");
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}
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