mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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254 lines
6.7 KiB
C
254 lines
6.7 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <unit/unit.h>
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#include <unit/io.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/fuse.h>
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#include "nvgpu-fuse-priv.h"
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#include "nvgpu-fuse-gp10b.h"
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#define GP10B_FUSE_REG_BASE 0x00021000U
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#define GP10B_FUSE_OPT_SEC_DEBUG_EN (GP10B_FUSE_REG_BASE+0x218U)
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#define GP10B_FUSE_OPT_ECC_EN (GP10B_FUSE_REG_BASE+0x228U)
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#define GP10B_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE \
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(GP10B_FUSE_REG_BASE+0x3f0U)
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#define GP10B_FUSE_OPT_PRIV_SEC_EN (GP10B_FUSE_REG_BASE+0x434U)
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/* for common init args */
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struct fuse_test_args gp10b_init_args = {
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.gpu_arch = 0x13,
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.gpu_impl = 0xb,
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.fuse_base_addr = GP10B_FUSE_REG_BASE,
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.sec_fuse_addr = GP10B_FUSE_OPT_PRIV_SEC_EN,
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};
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int test_fuse_gp10b_check_sec(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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int ret = UNIT_SUCCESS;
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int result;
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u32 i;
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nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x1);
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gcplex_config = GCPLEX_CONFIG_WPR_ENABLED_MASK &
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~GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK;
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for (i = 0; i < 2; i++) {
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nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_SEC_DEBUG_EN,
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i);
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result = g->ops.fuse.check_priv_security(g);
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if (result != 0) {
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unit_err(m, "%s: fuse_check_priv_security returned "
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"error %d\n", __func__, result);
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ret = UNIT_FAIL;
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}
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if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
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unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY disabled\n",
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__func__);
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ret = UNIT_FAIL;
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}
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if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
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unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS disabled\n",
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__func__);
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ret = UNIT_FAIL;
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}
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}
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return ret;
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}
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int test_fuse_gp10b_check_gcplex_fail(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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int ret = UNIT_SUCCESS;
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int result;
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g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_fail;
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result = g->ops.fuse.check_priv_security(g);
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if (result == 0) {
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unit_err(m, "%s: fuse_check_priv_security should have returned "
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" error\n", __func__);
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ret = UNIT_FAIL;
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}
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g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_pass;
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return ret;
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}
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int test_fuse_gp10b_check_sec_invalid_gcplex(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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int ret = UNIT_SUCCESS;
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int result;
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u32 gcplex_values[] = {
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0,
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~GCPLEX_CONFIG_WPR_ENABLED_MASK &
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GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK,
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GCPLEX_CONFIG_WPR_ENABLED_MASK |
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GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK,
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};
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int gcplex_entries = sizeof(gcplex_values)/sizeof(gcplex_values[0]);
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int i;
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g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_pass;
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nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x1);
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for (i = 0; i < gcplex_entries; i++) {
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gcplex_config = gcplex_values[i];
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result = g->ops.fuse.check_priv_security(g);
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if (result == 0) {
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unit_err(m, "%s: fuse_check_priv_security should have returned "
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"error, i = %d, gcplex_config = %x\n",
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__func__, i, gcplex_config);
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ret = UNIT_FAIL;
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}
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}
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return ret;
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}
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int test_fuse_gp10b_check_non_sec(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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int ret = UNIT_SUCCESS;
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int result;
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nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x0);
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result = g->ops.fuse.check_priv_security(g);
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if (result != 0) {
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unit_err(m, "%s: fuse_check_priv_security returned "
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"error %d\n", __func__, result);
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ret = UNIT_FAIL;
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}
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if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
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unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY enabled\n", __func__);
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ret = UNIT_FAIL;
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}
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if (nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
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unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS enabled\n", __func__);
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ret = UNIT_FAIL;
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}
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return ret;
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}
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int test_fuse_gp10b_ecc(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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bool result;
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int ret = UNIT_SUCCESS;
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nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_ECC_EN, 0x0);
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result = g->ops.fuse.is_opt_ecc_enable(g);
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if (result) {
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unit_err(m, "%s: ECC should be disabled\n", __func__);
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ret = UNIT_FAIL;
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}
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nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_ECC_EN, 0x1);
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result = g->ops.fuse.is_opt_ecc_enable(g);
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if (!result) {
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unit_err(m, "%s: ECC should be enabled\n", __func__);
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ret = UNIT_FAIL;
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}
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return ret;
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}
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int test_fuse_gp10b_feature_override_disable(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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bool result;
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int ret = UNIT_SUCCESS;
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nvgpu_posix_io_writel_reg_space(g,
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GP10B_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE, 0x0);
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result = g->ops.fuse.is_opt_feature_override_disable(g);
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if (result) {
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unit_err(m, "%s: Feature Override should be false\n", __func__);
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ret = UNIT_FAIL;
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}
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nvgpu_posix_io_writel_reg_space(g,
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GP10B_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE, 0x0);
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result = g->ops.fuse.is_opt_feature_override_disable(g);
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if (result) {
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unit_err(m, "%s: Feature Override should be true\n", __func__);
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ret = UNIT_FAIL;
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}
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return ret;
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}
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#ifdef CONFIG_NVGPU_SIM
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/* Verify when FMODEL is enabled, fuse module reports non-secure */
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int test_fuse_gp10b_check_fmodel(struct unit_module *m,
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struct gk20a *g, void *__args)
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{
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int ret = UNIT_SUCCESS;
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int result;
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nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
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result = g->ops.fuse.check_priv_security(g);
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if (result != 0) {
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unit_err(m, "%s: fuse_check_priv_security returned "
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"error %d\n", __func__, result);
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ret = UNIT_FAIL;
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}
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if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
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unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY enabled\n", __func__);
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ret = UNIT_FAIL;
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}
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if (nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
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unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS enabled\n", __func__);
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ret = UNIT_FAIL;
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}
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nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
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return ret;
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}
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#endif
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