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4c22d5c35d
gv11b onwards add hals
get_hwpm_gpcrouter_perfmon_regs_base
get_hwpm_fbprouter_perfmon_regs_base
And remove the ga10b version of same as that is redundant.
This is preparatory patch to update the gr_gv11b_pri_pmmgpcrouter_addr
and gr_gv11b_pri_pmmfbprouter_addr with the hals
JIRA NVGPU-9073
Change-Id: I8b04f9b61784ca2c09b248655435ea7a7ab92926
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2828584
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
77 lines
3.2 KiB
C
77 lines
3.2 KiB
C
/*
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* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GV11B_PERF
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#define NVGPU_GV11B_PERF
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#ifdef CONFIG_NVGPU_DEBUGGER
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_mem;
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bool gv11b_perf_get_membuf_overflow_status(struct gk20a *g);
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u32 gv11b_perf_get_membuf_pending_bytes(struct gk20a *g);
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void gv11b_perf_set_membuf_handled_bytes(struct gk20a *g,
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u32 entries, u32 entry_size);
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void gv11b_perf_membuf_reset_streaming(struct gk20a *g);
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void gv11b_perf_enable_membuf(struct gk20a *g, u32 size, u64 buf_addr);
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void gv11b_perf_disable_membuf(struct gk20a *g);
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void gv11b_perf_bind_mem_bytes_buffer_addr(struct gk20a *g, u64 buf_addr);
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int gv11b_perf_update_get_put(struct gk20a *g, u64 bytes_consumed, bool update_available_bytes,
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u64 *put_ptr, bool *overflowed);
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void gv11b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
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void gv11b_perf_deinit_inst_block(struct gk20a *g);
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u32 gv11b_perf_get_pmmsys_per_chiplet_offset(void);
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u32 gv11b_perf_get_pmmgpc_per_chiplet_offset(void);
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u32 gv11b_perf_get_pmmgpcrouter_per_chiplet_offset(void);
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u32 gv11b_perf_get_pmmfbp_per_chiplet_offset(void);
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u32 gv11b_perf_get_pmmfbprouter_per_chiplet_offset(void);
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u32 gv11b_get_hwpm_fbprouter_perfmon_regs_base(struct gk20a *g);
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u32 gv11b_get_hwpm_gpcrouter_perfmon_regs_base(struct gk20a *g);
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const u32 *gv11b_perf_get_hwpm_sys_perfmon_regs(u32 *count);
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const u32 *gv11b_perf_get_hwpm_gpc_perfmon_regs(u32 *count);
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const u32 *gv11b_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
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void gv11b_perf_set_pmm_register(struct gk20a *g, u32 offset, u32 val,
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u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons);
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void gv11b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
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u32 *num_fbp_perfmon, u32 *num_gpc_perfmon);
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void gv11b_perf_reset_hwpm_pmm_registers(struct gk20a *g);
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void gv11b_perf_init_hwpm_pmm_register(struct gk20a *g);
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void gv11b_perf_pma_stream_enable(struct gk20a *g, bool enable);
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void gv11b_perf_disable_all_perfmons(struct gk20a *g);
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int gv11b_perf_wait_for_idle_pmm_routers(struct gk20a *g);
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int gv11b_perf_wait_for_idle_pma(struct gk20a *g);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif
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