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9652764b65
Add new HAL g->ops.gr.reset_hwpm_pmm_registers() to reset all HWPM regs while binding HWPM in global mode in nvgpu_profiler_bind_hwpm() Add below new HALs to get sys/gpc/fbp register list and count g->ops.perf.get_hwpm_sys_perfmon_regs() g->ops.perf.get_hwpm_gpc_perfmon_regs() g->ops.perf.get_hwpm_fbp_perfmon_regs() Auto generate all the HWPM regs in below arrays for gv11b/tu104 static const u32 hwpm_sys_perfmon_regs[] static const u32 hwpm_gpc_perfmon_regs[] static const u32 hwpm_fbp_perfmon_regs[] Bug 2510974 Jira NVGPU-5360 Change-Id: I2ca5c04ed75c7b30ae942807bf018a24551d7ba0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2414934 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
263 lines
4.5 KiB
C
263 lines
4.5 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include "perf_tu104.h"
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static const u32 hwpm_sys_perfmon_regs[] =
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{
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/* This list is autogenerated. Do not edit. */
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0x00240000,
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0x00240004,
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0x00240008,
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0x0024000c,
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0x00240010,
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0x00240014,
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0x00240020,
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0x00240024,
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0x00240028,
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0x0024002c,
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0x00240030,
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0x00240034,
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0x00240040,
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0x00240044,
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0x00240048,
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0x0024004c,
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0x00240050,
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0x00240054,
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0x00240058,
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0x0024005c,
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0x00240060,
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0x00240064,
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0x00240068,
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0x0024006c,
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0x00240070,
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0x00240074,
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0x00240078,
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0x0024007c,
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0x00240080,
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0x00240084,
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0x00240088,
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0x0024008c,
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0x00240090,
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0x00240094,
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0x00240098,
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0x0024009c,
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0x002400a0,
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0x002400a4,
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0x002400a8,
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0x002400ac,
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0x002400b0,
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0x002400b4,
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0x002400b8,
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0x002400bc,
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0x002400c0,
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0x002400c4,
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0x002400c8,
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0x002400cc,
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0x002400d0,
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0x002400d4,
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0x002400d8,
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0x002400dc,
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0x002400e0,
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0x002400e4,
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0x002400e8,
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0x002400ec,
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0x002400f8,
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0x002400fc,
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0x00240104,
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0x00240108,
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0x0024010c,
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0x00240110,
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0x00240120,
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0x00240114,
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0x00240118,
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0x0024011c,
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0x00240124,
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0x00240100,
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};
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static const u32 hwpm_gpc_perfmon_regs[] =
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{
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/* This list is autogenerated. Do not edit. */
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0x00278000,
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0x00278004,
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0x00278008,
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0x0027800c,
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0x00278010,
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0x00278014,
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0x00278020,
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0x00278024,
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0x00278028,
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0x0027802c,
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0x00278030,
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0x00278034,
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0x00278040,
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0x00278044,
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0x00278048,
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0x0027804c,
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0x00278050,
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0x00278054,
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0x00278058,
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0x0027805c,
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0x00278060,
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0x00278064,
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0x00278068,
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0x0027806c,
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0x00278070,
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0x00278074,
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0x00278078,
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0x0027807c,
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0x00278080,
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0x00278084,
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0x00278088,
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0x0027808c,
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0x00278090,
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0x00278094,
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0x00278098,
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0x0027809c,
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0x002780a0,
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0x002780a4,
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0x002780a8,
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0x002780ac,
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0x002780b0,
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0x002780b4,
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0x002780b8,
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0x002780bc,
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0x002780c0,
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0x002780c4,
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0x002780c8,
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0x002780cc,
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0x002780d0,
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0x002780d4,
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0x002780d8,
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0x002780dc,
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0x002780e0,
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0x002780e4,
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0x002780e8,
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0x002780ec,
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0x002780f8,
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0x002780fc,
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0x00278104,
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0x00278108,
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0x0027810c,
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0x00278110,
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0x00278120,
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0x00278114,
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0x00278118,
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0x0027811c,
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0x00278124,
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0x00278100,
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};
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static const u32 hwpm_fbp_perfmon_regs[] =
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{
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/* This list is autogenerated. Do not edit. */
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0x0027c000,
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0x0027c004,
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0x0027c008,
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0x0027c00c,
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0x0027c010,
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0x0027c014,
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0x0027c020,
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0x0027c024,
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0x0027c028,
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0x0027c02c,
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0x0027c030,
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0x0027c034,
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0x0027c040,
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0x0027c044,
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0x0027c048,
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0x0027c04c,
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0x0027c050,
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0x0027c054,
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0x0027c058,
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0x0027c05c,
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0x0027c060,
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0x0027c064,
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0x0027c068,
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0x0027c06c,
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0x0027c070,
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0x0027c074,
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0x0027c078,
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0x0027c07c,
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0x0027c080,
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0x0027c084,
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0x0027c088,
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0x0027c08c,
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0x0027c090,
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0x0027c094,
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0x0027c098,
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0x0027c09c,
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0x0027c0a0,
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0x0027c0a4,
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0x0027c0a8,
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0x0027c0ac,
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0x0027c0b0,
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0x0027c0b4,
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0x0027c0b8,
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0x0027c0bc,
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0x0027c0c0,
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0x0027c0c4,
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0x0027c0c8,
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0x0027c0cc,
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0x0027c0d0,
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0x0027c0d4,
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0x0027c0d8,
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0x0027c0dc,
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0x0027c0e0,
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0x0027c0e4,
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0x0027c0e8,
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0x0027c0ec,
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0x0027c0f8,
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0x0027c0fc,
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0x0027c104,
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0x0027c108,
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0x0027c10c,
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0x0027c110,
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0x0027c120,
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0x0027c114,
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0x0027c118,
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0x0027c11c,
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0x0027c124,
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0x0027c100,
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};
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const u32 *tu104_perf_get_hwpm_sys_perfmon_regs(u32 *count)
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{
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*count = sizeof(hwpm_sys_perfmon_regs) / sizeof(hwpm_sys_perfmon_regs[0]);
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return hwpm_sys_perfmon_regs;
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}
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const u32 *tu104_perf_get_hwpm_gpc_perfmon_regs(u32 *count)
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{
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*count = sizeof(hwpm_gpc_perfmon_regs) / sizeof(hwpm_gpc_perfmon_regs[0]);
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return hwpm_gpc_perfmon_regs;
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}
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const u32 *tu104_perf_get_hwpm_fbp_perfmon_regs(u32 *count)
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{
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*count = sizeof(hwpm_fbp_perfmon_regs) / sizeof(hwpm_fbp_perfmon_regs[0]);
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return hwpm_fbp_perfmon_regs;
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}
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