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2ebf099207
JIRA DNVGPU-129 1)send 150'c as default temperature to PMU so that PMU will start reading temperature from sensor to evaluate VFE equations 2)Send GP106's temp min and max range for GPU sensor so that PMU will read right temperature 3)PMU will send event whenever temperature goes above +ve hysteresis or goes below -ve hysteresis. Call the Arbiter's VF re-evaluation function in the event handler. Change-Id: Iaebc0655f60e17998f0864824095f4fc8bba5b62 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1245392 (cherry picked from commit 7e59d0faa8cee6aace5524c724001e88248b2da7) Reviewed-on: http://git-master/r/1268062 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "perf.h"
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#include "pmuif/gpmuifperf.h"
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#include "pmuif/gpmuifperfvfe.h"
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#include "gk20a/pmu_gk20a.h"
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#include "clk/clk_arb.h"
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struct perfrpc_pmucmdhandler_params {
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struct nv_pmu_perf_rpc *prpccall;
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u32 success;
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};
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static void perfrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
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void *param, u32 handle, u32 status)
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{
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struct perfrpc_pmucmdhandler_params *phandlerparams =
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(struct perfrpc_pmucmdhandler_params *)param;
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gk20a_dbg_info("");
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if (msg->msg.perf.msg_type != NV_PMU_PERF_MSG_ID_RPC) {
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gk20a_err(dev_from_gk20a(g),
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"unsupported msg for VFE LOAD RPC %x",
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msg->msg.perf.msg_type);
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return;
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}
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if (phandlerparams->prpccall->b_supported)
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phandlerparams->success = 1;
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}
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static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg)
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{
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struct nv_pmu_perf_msg *msg = (struct nv_pmu_perf_msg *)pmu_msg;
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gk20a_dbg_fn("");
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switch (msg->msg_type) {
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case NV_PMU_PERF_MSG_ID_VFE_CALLBACK:
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nvgpu_clk_arb_schedule_vf_table_update(g);
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break;
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default:
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WARN_ON(1);
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break;
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}
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return 0;
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}
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u32 perf_pmu_vfe_load(struct gk20a *g)
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{
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struct pmu_cmd cmd;
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struct pmu_msg msg;
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struct pmu_payload payload = { {0} };
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u32 status;
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u32 seqdesc;
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struct nv_pmu_perf_rpc rpccall = {0};
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struct perfrpc_pmucmdhandler_params handler = {0};
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/*register call back for future VFE updates*/
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g->ops.perf.handle_pmu_perf_event = pmu_handle_perf_event;
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rpccall.function = NV_PMU_PERF_RPC_ID_VFE_LOAD;
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rpccall.params.vfe_load.b_load = true;
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cmd.hdr.unit_id = PMU_UNIT_PERF;
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cmd.hdr.size = (u32)sizeof(struct nv_pmu_perf_cmd) +
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(u32)sizeof(struct pmu_hdr);
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cmd.cmd.perf.cmd_type = NV_PMU_PERF_CMD_ID_RPC;
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msg.hdr.size = sizeof(struct pmu_msg);
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payload.in.buf = (u8 *)&rpccall;
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payload.in.size = (u32)sizeof(struct nv_pmu_perf_rpc);
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payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
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payload.in.offset = NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET;
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payload.out.buf = (u8 *)&rpccall;
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payload.out.size = (u32)sizeof(struct nv_pmu_perf_rpc);
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payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
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payload.out.offset = NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET;
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handler.prpccall = &rpccall;
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handler.success = 0;
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status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
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PMU_COMMAND_QUEUE_LPQ,
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perfrpc_pmucmdhandler, (void *)&handler,
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&seqdesc, ~0);
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if (status) {
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gk20a_err(dev_from_gk20a(g),
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"unable to post perf RPC cmd %x",
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cmd.cmd.perf.cmd_type);
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goto done;
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}
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pmu_wait_message_cond(&g->pmu,
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gk20a_get_gr_idle_timeout(g),
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&handler.success, 1);
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if (handler.success == 0) {
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status = -EINVAL;
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gk20a_err(dev_from_gk20a(g), "rpc call to load VFE failed");
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}
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done:
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return status;
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}
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