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b61a395106
Required for t19x ce isr handling JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: I18558d633012205f7e0920da65c8d9e89aab906d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1510290 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
28 lines
908 B
C
28 lines
908 B
C
/*
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* Pascal GPU series Copy Engine.
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*
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* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program.
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*/
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#ifndef __CE_GP10B_H__
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#define __CE_GP10B_H__
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#include "gk20a/channel_gk20a.h"
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#include "gk20a/tsg_gk20a.h"
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void gp10b_init_ce(struct gpu_ops *gops);
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void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
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#endif /*__CE2_GP10B_H__*/
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