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Name the Make and C flag variables consistently wih syntax: CONFIG_NVGPU_<feature name> s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS s/NVGPU_USERD/CONFIG_NVGPU_USERD s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU s/NVGPU_VPR/CONFIG_NVGPU_VPR s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG JIRA NVGPU-3624 Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130290 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
152 lines
3.8 KiB
C
152 lines
3.8 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvlink.h>
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#include <nvgpu/nvlink_link_mode_transitions.h>
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#ifdef CONFIG_NVGPU_NVLINK
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/*
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* WAR: use this function to find detault link, as only one is supported
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* on the library for now
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* Returns NVLINK_MAX_LINKS_SW on failure
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*/
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static u32 nvgpu_nvlink_get_link(struct gk20a *g)
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{
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u32 link_id;
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if (g == NULL) {
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return NVLINK_MAX_LINKS_SW;
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}
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/* Lets find the detected link */
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if (g->nvlink.initialized_links != 0U) {
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link_id = (u32)(ffs(g->nvlink.initialized_links) - 1UL);
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} else {
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return NVLINK_MAX_LINKS_SW;
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}
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if (g->nvlink.links[link_id].remote_info.is_connected) {
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return link_id;
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}
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return NVLINK_MAX_LINKS_SW;
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}
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enum nvgpu_nvlink_link_mode nvgpu_nvlink_get_link_mode(struct gk20a *g)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW) {
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return nvgpu_nvlink_link__last;
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}
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return g->ops.nvlink.link_mode_transitions.get_link_mode(g, link_id);
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}
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u32 nvgpu_nvlink_get_link_state(struct gk20a *g)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW) {
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/* 0xff is an undefined link_state */
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return U32_MAX;
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}
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return g->ops.nvlink.link_mode_transitions.get_link_state(g, link_id);
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}
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int nvgpu_nvlink_set_link_mode(struct gk20a *g,
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enum nvgpu_nvlink_link_mode mode)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW) {
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return -EINVAL;
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}
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return g->ops.nvlink.link_mode_transitions.set_link_mode(g, link_id,
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mode);
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}
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void nvgpu_nvlink_get_tx_sublink_state(struct gk20a *g, u32 *state)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW) {
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return;
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}
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if (state != NULL) {
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*state = g->ops.nvlink.link_mode_transitions.
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get_tx_sublink_state(g, link_id);
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}
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}
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void nvgpu_nvlink_get_rx_sublink_state(struct gk20a *g, u32 *state)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW) {
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return;
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}
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if (state != NULL) {
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*state = g->ops.nvlink.link_mode_transitions.
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get_rx_sublink_state(g, link_id);
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}
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}
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enum nvgpu_nvlink_sublink_mode nvgpu_nvlink_get_sublink_mode(struct gk20a *g,
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bool is_rx_sublink)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW) {
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return nvgpu_nvlink_sublink_rx__last;
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}
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return g->ops.nvlink.link_mode_transitions.get_sublink_mode(g,
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link_id, is_rx_sublink);
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}
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int nvgpu_nvlink_set_sublink_mode(struct gk20a *g,
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bool is_rx_sublink, enum nvgpu_nvlink_sublink_mode mode)
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{
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u32 link_id;
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link_id = nvgpu_nvlink_get_link(g);
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if (link_id == NVLINK_MAX_LINKS_SW) {
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return -EINVAL;
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}
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return g->ops.nvlink.link_mode_transitions.set_sublink_mode(g, link_id,
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is_rx_sublink, mode);
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}
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#endif
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