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b38f261981
Implemented parsing and sending performance table to pmu in form of Pstate board objs under Perf_pstate unit. NVGPU-3472 Change-Id: If8cc6373d1a03dd8f40a93a36203fa3d7127913f Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115564 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
63 lines
2.0 KiB
C
63 lines
2.0 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/clk_arb.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmu/perf.h>
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#include "pmu_perf.h"
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int nvgpu_perf_pmu_init_pmupstate(struct gk20a *g)
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{
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/* If already allocated, do not re-allocate */
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if (g->perf_pmu != NULL) {
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return 0;
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}
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g->perf_pmu = nvgpu_kzalloc(g, sizeof(*g->perf_pmu));
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if (g->perf_pmu == NULL) {
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return -ENOMEM;
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}
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return 0;
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}
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static void vfe_thread_stop_cb(void *data)
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{
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struct nvgpu_cond *cond = (struct nvgpu_cond *)data;
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nvgpu_cond_signal(cond);
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}
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void nvgpu_perf_pmu_free_pmupstate(struct gk20a *g)
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{
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if (nvgpu_thread_is_running(&g->perf_pmu->vfe_init.state_task)) {
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nvgpu_thread_stop_graceful(&g->perf_pmu->vfe_init.state_task,
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vfe_thread_stop_cb, &g->perf_pmu->vfe_init.wq);
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}
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nvgpu_cond_destroy(&g->perf_pmu->vfe_init.wq);
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nvgpu_kfree(g, g->perf_pmu);
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g->perf_pmu = NULL;
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}
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