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312f91f991
Move gk20a/fence_gk20a.c to common/fence/fence.c Renamed gk20a_fence_from_semaphore -> nvgpu_fence_from_semaphore gk20a_fence_from_syncpt -> nvgpu_fence_from_syncpt gk20a_alloc_fence_pool -> nvgpu_fence_pool_alloc gk20a_free_fence_pool -> nvgpu_fence_pool_free gk20a_alloc_fence -> nvgpu_fence_alloc gk20a_init_fence -> nvgpu_fence_init gk20a_fence_put -> nvgpu_fence_put gk20a_fence_get -> nvgpu_fence_get gk20a_fence_wait -> nvgpu_fence_wait gk20a_fence_is_expired -> nvgpu_fence_is_expired gk20a_fence_install_fd -> nvgpu_fence_install_fd gk20a_fence_ops struct -> nvgpu_fence_ops struct gk20a_fence struct -> nvgpu_fence_type struct JIRA NVGPU-1982 Change-Id: Ife77b2c3c386ff4368683c78ca02f00c99cddb4b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
/*
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*
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* Nvgpu Channel Synchronization Abstraction
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CHANNEL_SYNC_PRIV_H
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#define NVGPU_CHANNEL_SYNC_PRIV_H
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#include <nvgpu/atomic.h>
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#include <nvgpu/types.h>
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struct priv_cmd_entry;
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struct nvgpu_fence_type;
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/*
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* This struct is private and should not be used directly. Users should
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* instead use the public APIs starting with nvgpu_channel_sync_*
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*/
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struct nvgpu_channel_sync {
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nvgpu_atomic_t refcount;
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int (*wait_fence_raw)(struct nvgpu_channel_sync *s, u32 id, u32 thresh,
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struct priv_cmd_entry *entry);
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int (*wait_fence_fd)(struct nvgpu_channel_sync *s, int fd,
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struct priv_cmd_entry *entry, u32 max_wait_cmds);
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int (*incr)(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry *entry,
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struct nvgpu_fence_type *fence,
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bool need_sync_fence,
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bool register_irq);
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int (*incr_user)(struct nvgpu_channel_sync *s,
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int wait_fence_fd,
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struct priv_cmd_entry *entry,
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struct nvgpu_fence_type *fence,
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bool wfi,
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bool need_sync_fence,
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bool register_irq);
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void (*set_min_eq_max)(struct nvgpu_channel_sync *s);
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void (*set_safe_state)(struct nvgpu_channel_sync *s);
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void (*destroy)(struct nvgpu_channel_sync *s);
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};
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#endif /* NVGPU_CHANNEL_SYNC_PRIV_H */
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