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3f08cf8a48
Name the Make and C flag variables consistently wih syntax: CONFIG_NVGPU_<feature name> s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS s/NVGPU_USERD/CONFIG_NVGPU_USERD s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU s/NVGPU_VPR/CONFIG_NVGPU_VPR s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG JIRA NVGPU-3624 Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130290 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
120 lines
2.9 KiB
C
120 lines
2.9 KiB
C
/*
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* NVIDIA GPU HAL interface.
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/log.h>
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#include <nvgpu/hal_init.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/soc.h>
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#include "hal_gm20b.h"
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#include "hal_gp10b.h"
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#include "hal_gv11b.h"
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#ifdef CONFIG_NVGPU_DGPU
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#include "hal_tu104.h"
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#endif
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int nvgpu_init_hal(struct gk20a *g)
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{
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int err = 0;
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u32 ver = g->params.gpu_arch + g->params.gpu_impl;
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switch (ver) {
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case GK20A_GPUID_GM20B:
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nvgpu_log_info(g, "gm20b detected");
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if (gm20b_init_hal(g) != 0) {
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return -ENODEV;
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}
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break;
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case GK20A_GPUID_GM20B_B:
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nvgpu_log_info(g, "gm20b detected");
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if (gm20b_init_hal(g) != 0) {
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return -ENODEV;
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}
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break;
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case NVGPU_GPUID_GP10B:
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if (gp10b_init_hal(g) != 0) {
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return -ENODEV;
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}
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break;
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case NVGPU_GPUID_GV11B:
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if (gv11b_init_hal(g) != 0) {
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return -ENODEV;
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}
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break;
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#ifdef CONFIG_NVGPU_DGPU
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#if defined(CONFIG_NVGPU_SUPPORT_TURING)
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case NVGPU_GPUID_TU104:
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if (tu104_init_hal(g) != 0) {
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return -ENODEV;
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}
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break;
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#endif
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#endif
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default:
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nvgpu_err(g, "no support for %x", ver);
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err = -ENODEV;
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break;
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}
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return err;
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}
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int nvgpu_detect_chip(struct gk20a *g)
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{
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struct nvgpu_gpu_params *p = &g->params;
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u32 boot_0;
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int err;
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if (p->gpu_arch != 0U) {
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return 0;
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}
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boot_0 = nvgpu_mc_boot_0(g, &p->gpu_arch, &p->gpu_impl, &p->gpu_rev);
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if (boot_0 == U32_MAX) {
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nvgpu_err(g, "nvgpu_mc_boot_0 failure!");
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return -ENODEV;
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}
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if ((p->gpu_arch + p->gpu_impl) == (u32)NVGPU_GPUID_GV11B) {
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/* overwrite gpu revison for A02 */
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if (!nvgpu_is_soc_t194_a01(g)) {
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p->gpu_rev = 0xa2;
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}
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}
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nvgpu_log_info(g, "arch: %x, impl: %x, rev: %x\n",
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g->params.gpu_arch,
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g->params.gpu_impl,
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g->params.gpu_rev);
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err = nvgpu_init_hal(g);
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if (err != 0) {
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nvgpu_err(g, "nvgpu_init_hal failure!");
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return err;
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}
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return 0;
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}
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