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a3f3249c76
.load_timestamp_prod was defined protected by CONFIG_NVGPU_HAL_NON_FUSA and CONFIG_NVGPU_MIG. This patch moves the implementation of .load_timestamp_prod to the same macros. Jira GVSCI-9976 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Change-Id: I3204f3e7085d4098be2ab73e3b5300214ef04cfa Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2659002 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Aparna Das <aparnad@nvidia.com> GVS: Gerrit_Virtual_Submit
52 lines
2.1 KiB
C
52 lines
2.1 KiB
C
/*
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* GA10B GR MANAGER
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*
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* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GRMGR_GA10B_H
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#define NVGPU_GRMGR_GA10B_H
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struct gk20a;
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#ifdef CONFIG_NVGPU_MIG
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const struct nvgpu_mig_gpu_instance_config *ga10b_grmgr_get_mig_config_ptr(
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struct gk20a *g);
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u32 ga10b_grmgr_get_allowed_swizzid_size(struct gk20a *g);
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int ga10b_grmgr_init_gr_manager(struct gk20a *g);
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u32 ga10b_grmgr_get_max_sys_pipes(struct gk20a *g);
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int ga10b_grmgr_get_gpc_instance_gpcgrp_id(struct gk20a *g,
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u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id);
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int ga10b_grmgr_remove_gr_manager(struct gk20a *g);
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int ga10b_grmgr_get_mig_gpu_instance_config(struct gk20a *g,
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const char **config_name,
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u32 *num_config_supported);
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void ga10b_grmgr_get_gpcgrp_count(struct gk20a *g);
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#endif
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#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
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void ga10b_grmgr_load_smc_arb_timestamp_prod(struct gk20a *g);
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#endif
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int ga10b_grmgr_discover_gpc_ids(struct gk20a *g,
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u32 num_gpc, struct nvgpu_gpc *gpcs);
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#endif /* NVGPU_GRMGR_GA10B_H */
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