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a46abe4d64
10s wait for ACR timeout is longer than time allowed for entire GPU boot sequence. Hence we need to reduce it. This patch reduces ACR timeout wait period to 100msec for silicon platforms and retains the existing 10s for non silicon. JIRA NVGPU-4898 Change-Id: I29e58b34f09ed595336bf833ed6db13553794827 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2282857 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
152 lines
5.4 KiB
C
152 lines
5.4 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef ACR_H
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#define ACR_H
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#include "acr_bootstrap.h"
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#ifdef CONFIG_NVGPU_ACR_LEGACY
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#include "acr_blob_construct_v0.h"
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#endif
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#include "acr_blob_construct.h"
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struct gk20a;
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struct nvgpu_acr;
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struct wpr_carveout_info;
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#define nvgpu_acr_dbg(g, fmt, args...) \
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nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
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/*
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* Falcon UCODE header index.
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*/
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#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0U)
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#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1U)
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#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2U)
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#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3U)
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#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4U)
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/*
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* There are total N number of Apps with code and offset defined in UCODE header
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* This macro provides the CODE and DATA offset and size of Ath application.
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*/
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#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5U)
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#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2U))
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#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2U) + 1U)
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#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((N)*2U) - 1U)
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#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1U)
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#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2U))
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#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \
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(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2U) + 1U)
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#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((N)*2U) - 1U)
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#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1U)
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#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \
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(FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2U)
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#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
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#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
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#define HSBIN_ACR_AHESASC_NON_FUSA_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
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#define HSBIN_ACR_ASB_NON_FUSA_PROD_UCODE "acr_asb_prod_ucode.bin"
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#define HSBIN_ACR_AHESASC_NON_FUSA_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
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#define HSBIN_ACR_ASB_NON_FUSA_DBG_UCODE "acr_asb_dbg_ucode.bin"
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#define HSBIN_ACR_AHESASC_FUSA_PROD_UCODE "acr_ahesasc_fusa_prod_ucode.bin"
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#define HSBIN_ACR_ASB_FUSA_PROD_UCODE "acr_asb_fusa_prod_ucode.bin"
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#define HSBIN_ACR_AHESASC_FUSA_DBG_UCODE "acr_ahesasc_fusa_dbg_ucode.bin"
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#define HSBIN_ACR_ASB_FUSA_DBG_UCODE "acr_asb_fusa_dbg_ucode.bin"
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#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
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#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
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#define TU104_FECS_UCODE_SIG "tu104/fecs_sig.bin"
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#define TU104_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin"
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#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin"
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#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin"
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#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin"
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#define LSF_SEC2_UCODE_IMAGE_FUSA_BIN "sec2_ucode_fusa_image.bin"
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#define LSF_SEC2_UCODE_DESC_FUSA_BIN "sec2_ucode_fusa_desc.bin"
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#define LSF_SEC2_UCODE_SIG_FUSA_BIN "sec2_fusa_sig.bin"
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#define ACR_COMPLETION_TIMEOUT_NON_SILICON_MS 10000U /*in msec */
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#define ACR_COMPLETION_TIMEOUT_SILICON_MS 100 /*in msec */
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struct acr_lsf_config {
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u32 falcon_id;
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u32 falcon_dma_idx;
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bool is_lazy_bootstrap;
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bool is_priv_load;
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int (*get_lsf_ucode_details)(struct gk20a *g, void *lsf_ucode_img);
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void (*get_cmd_line_args_offset)(struct gk20a *g, u32 *args_offset);
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};
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struct nvgpu_acr {
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struct gk20a *g;
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u32 bootstrap_owner;
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/* LSF properties */
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u64 lsf_enable_mask;
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struct acr_lsf_config lsf[FALCON_ID_END];
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/*
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* non-wpr space to hold LSF ucodes,
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* ACR does copy ucode from non-wpr to wpr
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*/
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struct nvgpu_mem ucode_blob;
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/*
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* Even though this mem_desc wouldn't be used,
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* the wpr region needs to be reserved in the
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* allocator in dGPU case.
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*/
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struct nvgpu_mem wpr_dummy;
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/* ACR member for different types of ucode */
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/* For older dgpu/tegra ACR cuode */
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struct hs_acr acr;
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/* ACR load split feature support */
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struct hs_acr acr_ahesasc;
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struct hs_acr acr_asb;
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int (*prepare_ucode_blob)(struct gk20a *g);
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int (*alloc_blob_space)(struct gk20a *g, size_t size,
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struct nvgpu_mem *mem);
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void (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc, bool is_recovery);
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int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr);
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void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf);
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};
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#endif /* ACR_H */
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