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The trivial ringbuffer implementation in channel job list and priv cmd buffers acts such that the buffer is full when the number of inserted entries in it is one less than allocation size, similarly to the hardware gpfifo. Take this into account when allocating the job tracking resources: previously the allocation has been off-by-one too small. Jira NVGPU-5492 Change-Id: If7bfd4919daa5b0328394ca289d5692c0d2b4f5f Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342129 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
234 lines
6.1 KiB
C
234 lines
6.1 KiB
C
/*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/circ_buf.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/job.h>
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#include <nvgpu/priv_cmdbuf.h>
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#include <nvgpu/fence.h>
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static inline struct nvgpu_channel_job *
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channel_gk20a_job_from_list(struct nvgpu_list_node *node)
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{
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return (struct nvgpu_channel_job *)
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((uintptr_t)node - offsetof(struct nvgpu_channel_job, list));
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};
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int nvgpu_channel_alloc_job(struct nvgpu_channel *c,
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struct nvgpu_channel_job **job_out)
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{
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int err = 0;
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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unsigned int put = c->joblist.pre_alloc.put;
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unsigned int get = c->joblist.pre_alloc.get;
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unsigned int next = (put + 1) % c->joblist.pre_alloc.length;
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bool full = next == get;
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/*
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* ensure all subsequent reads happen after reading get.
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* see corresponding nvgpu_smp_wmb in
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* nvgpu_channel_clean_up_jobs()
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*/
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nvgpu_smp_rmb();
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if (!full) {
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*job_out = &c->joblist.pre_alloc.jobs[put];
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} else {
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nvgpu_warn(c->g,
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"out of job ringbuffer space");
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err = -EAGAIN;
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}
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} else {
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*job_out = nvgpu_kzalloc(c->g,
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sizeof(struct nvgpu_channel_job));
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if (*job_out == NULL) {
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err = -ENOMEM;
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}
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}
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return err;
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}
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void nvgpu_channel_free_job(struct nvgpu_channel *c,
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struct nvgpu_channel_job *job)
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{
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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(void) memset(job, 0, sizeof(*job));
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} else {
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nvgpu_kfree(c->g, job);
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}
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}
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void nvgpu_channel_joblist_lock(struct nvgpu_channel *c)
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{
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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nvgpu_mutex_acquire(&c->joblist.pre_alloc.read_lock);
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} else {
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nvgpu_spinlock_acquire(&c->joblist.dynamic.lock);
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}
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}
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void nvgpu_channel_joblist_unlock(struct nvgpu_channel *c)
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{
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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nvgpu_mutex_release(&c->joblist.pre_alloc.read_lock);
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} else {
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nvgpu_spinlock_release(&c->joblist.dynamic.lock);
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}
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}
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struct nvgpu_channel_job *channel_joblist_peek(struct nvgpu_channel *c)
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{
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u32 get;
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struct nvgpu_channel_job *job = NULL;
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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if (!nvgpu_channel_joblist_is_empty(c)) {
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get = c->joblist.pre_alloc.get;
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job = &c->joblist.pre_alloc.jobs[get];
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}
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} else {
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if (!nvgpu_list_empty(&c->joblist.dynamic.jobs)) {
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job = nvgpu_list_first_entry(&c->joblist.dynamic.jobs,
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channel_gk20a_job, list);
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}
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}
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return job;
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}
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void channel_joblist_add(struct nvgpu_channel *c,
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struct nvgpu_channel_job *job)
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{
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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c->joblist.pre_alloc.put = (c->joblist.pre_alloc.put + 1U) %
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(c->joblist.pre_alloc.length);
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} else {
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nvgpu_list_add_tail(&job->list, &c->joblist.dynamic.jobs);
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}
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}
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void channel_joblist_delete(struct nvgpu_channel *c,
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struct nvgpu_channel_job *job)
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{
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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c->joblist.pre_alloc.get = (c->joblist.pre_alloc.get + 1U) %
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(c->joblist.pre_alloc.length);
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} else {
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nvgpu_list_del(&job->list);
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}
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}
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bool nvgpu_channel_joblist_is_empty(struct nvgpu_channel *c)
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{
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if (nvgpu_channel_is_prealloc_enabled(c)) {
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unsigned int get = c->joblist.pre_alloc.get;
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unsigned int put = c->joblist.pre_alloc.put;
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return get == put;
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}
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return nvgpu_list_empty(&c->joblist.dynamic.jobs);
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}
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int channel_prealloc_resources(struct nvgpu_channel *ch, u32 num_jobs)
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{
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#ifdef CONFIG_NVGPU_DETERMINISTIC_CHANNELS
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int err;
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u32 size;
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if ((nvgpu_channel_is_prealloc_enabled(ch)) || (num_jobs == 0U)) {
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return -EINVAL;
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}
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size = (u32)sizeof(struct nvgpu_channel_job);
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if (num_jobs > nvgpu_safe_sub_u32(U32_MAX / size, 1U)) {
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err = -ERANGE;
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goto clean_up;
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}
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/*
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* The max capacity of this ring buffer is the alloc size minus one (in
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* units of item slot), so allocate a size of (num_jobs + 1) * size
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* bytes.
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*/
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ch->joblist.pre_alloc.jobs = nvgpu_vzalloc(ch->g,
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nvgpu_safe_mult_u32(
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nvgpu_safe_add_u32(num_jobs, 1U),
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size));
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if (ch->joblist.pre_alloc.jobs == NULL) {
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err = -ENOMEM;
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goto clean_up;
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}
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/* pre-allocate a fence pool */
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err = nvgpu_fence_pool_alloc(ch, num_jobs);
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if (err != 0) {
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goto clean_up;
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}
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ch->joblist.pre_alloc.length = num_jobs;
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ch->joblist.pre_alloc.put = 0;
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ch->joblist.pre_alloc.get = 0;
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/*
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* commit the previous writes before setting the flag.
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* see corresponding nvgpu_smp_rmb in
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* nvgpu_channel_is_prealloc_enabled()
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*/
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nvgpu_smp_wmb();
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ch->joblist.pre_alloc.enabled = true;
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return 0;
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clean_up:
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nvgpu_vfree(ch->g, ch->joblist.pre_alloc.jobs);
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(void) memset(&ch->joblist.pre_alloc, 0, sizeof(ch->joblist.pre_alloc));
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return err;
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#else
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return -ENOSYS;
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#endif
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}
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void channel_free_prealloc_resources(struct nvgpu_channel *c)
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{
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#ifdef CONFIG_NVGPU_DETERMINISTIC_CHANNELS
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nvgpu_vfree(c->g, c->joblist.pre_alloc.jobs[0].wait_cmd);
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nvgpu_vfree(c->g, c->joblist.pre_alloc.jobs);
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nvgpu_fence_pool_free(c);
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/*
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* commit the previous writes before disabling the flag.
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* see corresponding nvgpu_smp_rmb in
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* nvgpu_channel_is_prealloc_enabled()
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*/
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nvgpu_smp_wmb();
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c->joblist.pre_alloc.enabled = false;
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#endif
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}
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