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a6cbfca58c
Fix the following MISRA rule violations in bitops unit, MISRA Rule 10.1 MISRA Rule 10.3 MISRA Rule 10.4 MISRA Rule 11.8 MISRA Rule 21.2 Introduce nvgpu specific functions for bitops and bitmap operations with unsigned integer as parameter for offset. OS specific type conversions and handling of these inerfaces are taken care in the respective OS files. Jira NVGPU-3545 Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c Signed-off-by: ajesh <akv@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2129513 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
92 lines
3.3 KiB
C
92 lines
3.3 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_POSIX_BITOPS_H
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#define NVGPU_POSIX_BITOPS_H
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#include <nvgpu/types.h>
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/*
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* Assume an 8 bit byte, of course.
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*/
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#define BITS_PER_BYTE 8UL
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#define BITS_PER_LONG ((unsigned long)__SIZEOF_LONG__ * BITS_PER_BYTE)
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#define BITS_TO_LONGS(bits) \
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(((bits) + BITS_PER_LONG - 1UL) / BITS_PER_LONG)
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/*
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* Deprecated; use the explicit BITxx() macros instead.
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*/
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#define BIT(i) BIT64(i)
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#define GENMASK(hi, lo) \
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(((~0UL) - (1UL << (lo)) + 1UL) & \
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(~0UL >> (BITS_PER_LONG - 1UL - (unsigned long)(hi))))
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#define DECLARE_BITMAP(bmap, bits) \
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unsigned long bmap[BITS_TO_LONGS(bits)]
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#define for_each_set_bit(bit, addr, size) \
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for ((bit) = find_first_bit((addr), (size)); \
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(bit) < (size); \
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(bit) = find_next_bit((addr), (size), (bit) + 1U))
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unsigned long nvgpu_posix_ffs(unsigned long word);
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unsigned long nvgpu_posix_fls(unsigned long word);
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#define ffs(word) nvgpu_posix_ffs(word)
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#define fls(word) nvgpu_posix_fls(word)
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#define ffz(word) (ffs(~(word)) - 1UL)
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unsigned long find_first_bit(const unsigned long *addr, unsigned long size);
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unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
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unsigned long offset);
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unsigned long find_first_zero_bit(const unsigned long *addr,
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unsigned long size);
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bool nvgpu_test_bit(unsigned int nr, const volatile unsigned long *addr);
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bool nvgpu_test_and_set_bit(unsigned int nr, volatile unsigned long *addr);
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bool nvgpu_test_and_clear_bit(unsigned int nr, volatile unsigned long *addr);
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/*
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* These two are atomic.
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*/
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void nvgpu_set_bit(unsigned int nr, volatile unsigned long *addr);
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void nvgpu_clear_bit(unsigned int nr, volatile unsigned long *addr);
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void nvgpu_bitmap_set(unsigned long *map, unsigned int start, unsigned int len);
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void nvgpu_bitmap_clear(unsigned long *map, unsigned int start, unsigned int len);
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unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
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unsigned long size,
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unsigned long start,
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unsigned int nr,
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unsigned long align_mask,
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unsigned long align_offset);
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unsigned long bitmap_find_next_zero_area(unsigned long *map,
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unsigned long size,
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unsigned long start,
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unsigned int nr,
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unsigned long align_mask);
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#endif /* NVGPU_POSIX_BITOPS_H */
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