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a759ee0ec8
Fetch DMEM size of PMU falcon using common Falcon interface to copy PMU ucode command lines args at top of PMU DMEM offset. Change needed to cleanup dependency between PMU and ACR JIRA NVGPU-1147 Change-Id: Ie0b1bcf0bdd1afb2c37c1a7d061dc9b03f9fc679 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012082 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
189 lines
6.6 KiB
C
189 lines
6.6 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FALCON_H
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#define NVGPU_FALCON_H
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#include <nvgpu/types.h>
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/*
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* Falcon Id Defines
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*/
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#define FALCON_ID_PMU (0U)
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#define FALCON_ID_GSPLITE (1U)
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#define FALCON_ID_FECS (2U)
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#define FALCON_ID_GPCCS (3U)
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#define FALCON_ID_NVDEC (4U)
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#define FALCON_ID_SEC2 (7U)
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#define FALCON_ID_MINION (10U)
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#define FALCON_ID_END (11U)
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#define FALCON_ID_INVALID 0xFFFFFFFFU
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#define FALCON_MAILBOX_0 0x0U
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#define FALCON_MAILBOX_1 0x1U
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#define FALCON_MAILBOX_COUNT 0x02U
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#define FALCON_BLOCK_SIZE 0x100U
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#define GET_IMEM_TAG(IMEM_ADDR) ((IMEM_ADDR) >> 8U)
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#define GET_NEXT_BLOCK(ADDR) \
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(((((ADDR) + (FALCON_BLOCK_SIZE - 1U)) & ~(FALCON_BLOCK_SIZE-1U)) \
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/ FALCON_BLOCK_SIZE) << 8U)
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/* Falcon ucode header format
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* OS Code Offset
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* OS Code Size
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* OS Data Offset
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* OS Data Size
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* NumApps (N)
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* App 0 Code Offset
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* App 0 Code Size
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* . . . .
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* App N - 1 Code Offset
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* App N - 1 Code Size
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* App 0 Data Offset
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* App 0 Data Size
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* . . . .
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* App N - 1 Data Offset
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* App N - 1 Data Size
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* OS Ovl Offset
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* OS Ovl Size
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*/
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#define OS_CODE_OFFSET 0x0U
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#define OS_CODE_SIZE 0x1U
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#define OS_DATA_OFFSET 0x2U
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#define OS_DATA_SIZE 0x3U
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#define NUM_APPS 0x4U
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#define APP_0_CODE_OFFSET 0x5U
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#define APP_0_CODE_SIZE 0x6U
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/* Queue Type */
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#define QUEUE_TYPE_DMEM 0x0U
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#define QUEUE_TYPE_EMEM 0x1U
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#define QUEUE_TYPE_FB 0x2U
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struct gk20a;
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struct nvgpu_falcon;
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struct nvgpu_falcon_queue;
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struct nvgpu_falcon_queue_params {
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/* Queue Type (queue_type) */
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u8 queue_type;
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/* current write position */
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u32 position;
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/* physical dmem offset where this queue begins */
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u32 offset;
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/* logical queue identifier */
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u32 id;
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/* physical queue index */
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u32 index;
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/* in bytes */
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u32 size;
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/* open-flag */
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u32 oflag;
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/* fb queue params*/
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/* Holds the offset of queue data (0th element) */
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u32 fbq_offset;
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/* fb queue element size*/
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u32 fbq_element_size;
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/* Holds super surface base address */
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struct nvgpu_mem *super_surface_mem;
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};
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struct nvgpu_falcon_bl_info {
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void *bl_src;
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u8 *bl_desc;
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u32 bl_desc_size;
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u32 bl_size;
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u32 bl_start_tag;
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};
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int nvgpu_falcon_wait_idle(struct nvgpu_falcon *flcn);
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int nvgpu_falcon_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout);
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int nvgpu_falcon_clear_halt_intr_status(struct nvgpu_falcon *flcn,
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unsigned int timeout);
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int nvgpu_falcon_reset(struct nvgpu_falcon *flcn);
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void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
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u32 intr_mask, u32 intr_dest);
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int nvgpu_falcon_mem_scrub_wait(struct nvgpu_falcon *flcn);
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int nvgpu_falcon_copy_from_emem(struct nvgpu_falcon *flcn,
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u32 src, u8 *dst, u32 size, u8 port);
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int nvgpu_falcon_copy_to_emem(struct nvgpu_falcon *flcn,
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u32 dst, u8 *src, u32 size, u8 port);
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int nvgpu_falcon_copy_from_dmem(struct nvgpu_falcon *flcn,
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u32 src, u8 *dst, u32 size, u8 port);
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int nvgpu_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
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u32 dst, u8 *src, u32 size, u8 port);
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int nvgpu_falcon_copy_to_imem(struct nvgpu_falcon *flcn,
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u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag);
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int nvgpu_falcon_copy_from_imem(struct nvgpu_falcon *flcn,
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u32 src, u8 *dst, u32 size, u8 port);
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u32 nvgpu_falcon_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index);
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void nvgpu_falcon_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index,
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u32 data);
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int nvgpu_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
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void nvgpu_falcon_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size);
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void nvgpu_falcon_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size);
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void nvgpu_falcon_dump_stats(struct nvgpu_falcon *flcn);
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int nvgpu_falcon_bl_bootstrap(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_bl_info *bl_info);
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void nvgpu_falcon_get_ctls(struct nvgpu_falcon *flcn, u32 *sctl, u32 *cpuctl);
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int nvgpu_falcon_get_dmem_size(struct nvgpu_falcon *flcn, u32 *dmem_size);
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struct gk20a *nvgpu_falcon_to_gk20a(struct nvgpu_falcon *flcn);
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u32 nvgpu_falcon_get_id(struct nvgpu_falcon *flcn);
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/* queue public functions */
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int nvgpu_falcon_queue_init(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_queue **queue_p,
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struct nvgpu_falcon_queue_params params);
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bool nvgpu_falcon_queue_is_empty(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_queue *queue);
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int nvgpu_falcon_queue_rewind(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_queue *queue);
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int nvgpu_falcon_queue_pop(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_queue *queue, void *data, u32 size,
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u32 *bytes_read);
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int nvgpu_falcon_queue_push(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_queue *queue, void *data, u32 size);
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void nvgpu_falcon_queue_free(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_queue **queue_p);
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u32 nvgpu_falcon_queue_get_id(struct nvgpu_falcon_queue *queue);
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u32 nvgpu_falcon_queue_get_position(struct nvgpu_falcon_queue *queue);
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u32 nvgpu_falcon_queue_get_index(struct nvgpu_falcon_queue *queue);
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u32 nvgpu_falcon_queue_get_size(struct nvgpu_falcon_queue *queue);
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u32 nvgpu_falcon_fbq_get_element_size(struct nvgpu_falcon_queue *queue);
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u32 nvgpu_falcon_queue_get_fbq_offset(struct nvgpu_falcon_queue *queue);
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u8 *nvgpu_falcon_queue_get_fbq_work_buffer(struct nvgpu_falcon_queue *queue);
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int nvgpu_falcon_queue_free_fbq_element(struct nvgpu_falcon *flcn,
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struct nvgpu_falcon_queue *queue, u32 queue_pos);
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void nvgpu_falcon_queue_lock_fbq_work_buffer(struct nvgpu_falcon_queue *queue);
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void nvgpu_falcon_queue_unlock_fbq_work_buffer(
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struct nvgpu_falcon_queue *queue);
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int nvgpu_falcon_sw_init(struct gk20a *g, u32 flcn_id);
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void nvgpu_falcon_sw_free(struct gk20a *g, u32 flcn_id);
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#endif /* NVGPU_FALCON_H */
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