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b40c655e12
Move regops (gk20a/regops_gk20a.c) to separate unit common/regops/regops.c Move corresponding header (gk20a/regops_gk20a.h) to include/nvgpu/regops.h Move rest of the platform HAL files to common/regops/ as well Fix all the header includes to include new public header Remove *_apply_smpc_war() declarations from headers. Corresponding functions were cleaned up already, and declarations were left somehow Jira NVGPU-620 Change-Id: I8b8065b9c91f69809bdeb1b4caecdc7582c8a992 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1998723 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
42 lines
1.9 KiB
C
42 lines
1.9 KiB
C
/*
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*
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* Tegra GP10B GPU Debugger Driver Register Ops
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_REGOPS_GP10B_H
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#define NVGPU_REGOPS_GP10B_H
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const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void);
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u64 gp10b_get_global_whitelist_ranges_count(void);
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const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void);
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u64 gp10b_get_context_whitelist_ranges_count(void);
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const u32 *gp10b_get_runcontrol_whitelist(void);
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u64 gp10b_get_runcontrol_whitelist_count(void);
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const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void);
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u64 gp10b_get_runcontrol_whitelist_ranges_count(void);
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const u32 *gp10b_get_qctl_whitelist(void);
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u64 gp10b_get_qctl_whitelist_count(void);
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const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
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u64 gp10b_get_qctl_whitelist_ranges_count(void);
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#endif /* NVGPU_REGOPS_GP10B_H */
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