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5efc446a06
With intention to make falcon header free of private data we are making all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn, nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct nvgpu_falcon. Falcon structures are allocated/deallocated by falcon_sw_init & _free respectively. While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn, refactor flcn_id assignment and introduce falcon_hal_sw_free. JIRA NVGPU-1594 Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1968242 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
119 lines
3.8 KiB
C
119 lines
3.8 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/falcon.h>
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#include <nvgpu/io.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/gk20a.h>
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#include "gv100/gsp_gv100.h"
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#include <nvgpu/hw/gv100/hw_pgsp_gv100.h>
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int gv100_gsp_reset(struct gk20a *g)
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{
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gk20a_writel(g, pgsp_falcon_engine_r(),
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pgsp_falcon_engine_reset_true_f());
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nvgpu_udelay(10);
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gk20a_writel(g, pgsp_falcon_engine_r(),
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pgsp_falcon_engine_reset_false_f());
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return 0;
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}
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static int gsp_flcn_bl_bootstrap(struct gk20a *g,
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struct nvgpu_falcon_bl_info *bl_info)
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{
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struct mm_gk20a *mm = &g->mm;
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u32 data = 0;
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u32 status = 0;
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gk20a_writel(g, pgsp_falcon_itfen_r(),
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gk20a_readl(g, pgsp_falcon_itfen_r()) |
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pgsp_falcon_itfen_ctxen_enable_f());
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gk20a_writel(g, pgsp_falcon_nxtctx_r(),
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pgsp_falcon_nxtctx_ctxptr_f(
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nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) |
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pgsp_falcon_nxtctx_ctxvalid_f(1) |
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nvgpu_aperture_mask(g, &mm->pmu.inst_block,
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pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(),
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pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(),
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pgsp_falcon_nxtctx_ctxtgt_fb_f()));
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data = gk20a_readl(g, pgsp_falcon_debug1_r());
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data |= pgsp_falcon_debug1_ctxsw_mode_m();
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gk20a_writel(g, pgsp_falcon_debug1_r(), data);
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data = gk20a_readl(g, pgsp_falcon_engctl_r());
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data |= pgsp_falcon_engctl_switch_context_true_f();
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gk20a_writel(g, pgsp_falcon_engctl_r(), data);
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status = nvgpu_falcon_bl_bootstrap(g->gsp_flcn, bl_info);
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return status;
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}
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int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g,
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struct hs_acr *acr_desc,
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struct nvgpu_falcon_bl_info *bl_info)
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{
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u32 data = 0;
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int err = 0;
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err = nvgpu_falcon_reset(g->gsp_flcn);
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if (err != 0) {
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goto exit;
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}
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data = gk20a_readl(g, pgsp_fbif_ctl_r());
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data |= pgsp_fbif_ctl_allow_phys_no_ctx_allow_f();
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gk20a_writel(g, pgsp_fbif_ctl_r(), data);
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/* setup apertures - virtual */
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gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
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pgsp_fbif_transcfg_mem_type_physical_f() |
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pgsp_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
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pgsp_fbif_transcfg_mem_type_virtual_f());
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/* setup apertures - physical */
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gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
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pgsp_fbif_transcfg_mem_type_physical_f() |
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pgsp_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
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pgsp_fbif_transcfg_mem_type_physical_f() |
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pgsp_fbif_transcfg_target_coherent_sysmem_f());
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gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
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pgsp_fbif_transcfg_mem_type_physical_f() |
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pgsp_fbif_transcfg_target_noncoherent_sysmem_f());
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err = gsp_flcn_bl_bootstrap(g, bl_info);
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exit:
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return err;
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}
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u32 gv100_gsp_falcon_base_addr(void)
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{
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return pgsp_falcon_irqsset_r();
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}
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