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254253732c
Add new unit common/gr/subctx.c to manage GR subcontext This unit provides interfaces to allocate/free/load GR subcontext Add new header file include/nvgpu/gr/subctx.h to declare all the interfaces. Right now channel_gk20a structure directly includes a nvgpu_mem for context header. Declare a new structure nvgpu_gr_subctx for subcontext and include this from channel_gk20a Make all necessary changes to refer ctx_header from subctx instead of directly referencing it from channel Jira NVGPU-1613 Change-Id: I9eb1ee8f26fa88d2881f9b294935b65e9cbcc9b4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1990129 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
114 lines
3.7 KiB
C
114 lines
3.7 KiB
C
/*
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* Volta GPU series Subcontext
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*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/log.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/gr/subctx.h>
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#include <nvgpu/gr/ctx.h>
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#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
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#include "gv11b/subctx_gv11b.h"
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static void gv11b_subctx_commit_valid_mask(struct vm_gk20a *vm,
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struct nvgpu_mem *inst_block);
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static void gv11b_subctx_commit_pdb(struct vm_gk20a *vm,
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struct nvgpu_mem *inst_block,
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bool replayable);
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void gv11b_free_subctx_header(struct channel_gk20a *c)
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{
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if (c->subctx != NULL) {
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nvgpu_gr_subctx_free(c->g, c->subctx, c->vm);
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}
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}
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void gv11b_init_subcontext_pdb(struct vm_gk20a *vm,
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struct nvgpu_mem *inst_block,
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bool replayable)
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{
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gv11b_subctx_commit_pdb(vm, inst_block, replayable);
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gv11b_subctx_commit_valid_mask(vm, inst_block);
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}
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static void gv11b_subctx_commit_valid_mask(struct vm_gk20a *vm,
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struct nvgpu_mem *inst_block)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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/* Make all subctx pdbs valid */
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nvgpu_mem_wr32(g, inst_block, 166, 0xffffffffU);
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nvgpu_mem_wr32(g, inst_block, 167, 0xffffffffU);
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}
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static void gv11b_subctx_commit_pdb(struct vm_gk20a *vm,
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struct nvgpu_mem *inst_block,
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bool replayable)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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u32 lo, hi;
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u32 subctx_id = 0;
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u32 format_word;
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u32 pdb_addr_lo, pdb_addr_hi;
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u64 pdb_addr;
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u32 max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v();
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u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem,
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ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(),
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ram_in_sc_page_dir_base_target_sys_mem_coh_v(),
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ram_in_sc_page_dir_base_target_vid_mem_v());
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pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem);
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pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
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pdb_addr_hi = u64_hi32(pdb_addr);
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format_word = ram_in_sc_page_dir_base_target_f(
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aperture, 0) |
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ram_in_sc_page_dir_base_vol_f(
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ram_in_sc_page_dir_base_vol_true_v(), 0) |
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ram_in_sc_use_ver2_pt_format_f(1, 0) |
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ram_in_sc_big_page_size_f(1, 0) |
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ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
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if (replayable) {
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format_word |=
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ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) |
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ram_in_sc_page_dir_base_fault_replay_gcc_f(1, 0);
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}
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nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x",
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format_word, pdb_addr_hi);
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for (subctx_id = 0U; subctx_id < max_subctx_count; subctx_id++) {
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lo = ram_in_sc_page_dir_base_vol_0_w() + (4U * subctx_id);
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hi = ram_in_sc_page_dir_base_hi_0_w() + (4U * subctx_id);
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nvgpu_mem_wr32(g, inst_block, lo, format_word);
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nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi);
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}
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}
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