mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
cef9b8ff9d
This adds the initial unit test for the fuse module and testing for gp10b. It verifies the exposed APIs for this device in the fuse module. To allow the hal_init to pass before the HAL for read_gcplex_config_fuse() can be overridden, the default behavior of the POSIX implementation for nvgpu_tegra_fuse_read_gcplex_config_fuse() is changed. This provides 100% code and branch coverage for this unit/device. JIRA NVGPU-938 Change-Id: I9efa8080c12ace637581c77aa35aab3f86a94760 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1943385 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/*
|
|
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/fuse.h>
|
|
|
|
int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
|
|
{
|
|
}
|
|
|
|
void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
|
|
{
|
|
}
|
|
|
|
void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
|
|
{
|
|
}
|
|
|
|
void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
|
|
{
|
|
}
|
|
|
|
int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
|
|
{
|
|
*val = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
|
|
{
|
|
return -ENODEV;
|
|
}
|