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800d96865d
MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed by brackets. This patch adds brackets to single line if/else/loop blocks in the POSIX code. JIRA NVGPU-775 Change-Id: Idafd5a5068c23b850ad1b0b083550a75b35588c1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2011739 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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/*
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* Define a length for log buffers. This is the buffer that the 'fmt, ...' part
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* of __nvgpu_do_log_print() prints into.
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*/
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#define LOG_BUFFER_LENGTH 160
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/*
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* Keep this roughly the same as the kernel log format.
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*/
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#define LOG_FMT "nvgpu: %s %33s:%-4d [%-4s] %s\n"
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u64 nvgpu_dbg_mask = NVGPU_DEFAULT_DBG_MASK;
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static const char *log_types[] = {
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"ERR",
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"WRN",
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"DBG",
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"INFO",
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};
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static inline const char *nvgpu_log_name(struct gk20a *g)
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{
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return "gpu.USS";
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}
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bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask)
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{
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return (g->log_mask & log_mask) != 0ULL;
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}
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static void __nvgpu_really_print_log(const char *gpu_name,
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const char *func_name, int line,
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enum nvgpu_log_type type, const char *log)
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{
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const char *name = gpu_name ? gpu_name : "";
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const char *log_type = log_types[type];
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printf(LOG_FMT, name, func_name, line, log_type, log);
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}
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
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enum nvgpu_log_type type, const char *fmt, ...)
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{
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char log[LOG_BUFFER_LENGTH];
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va_list args;
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va_start(args, fmt);
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(void) vsnprintf(log, LOG_BUFFER_LENGTH, fmt, args);
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va_end(args);
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__nvgpu_really_print_log(nvgpu_log_name(g),
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func_name, line, type, log);
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}
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
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const char *func_name, int line,
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const char *fmt, ...)
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{
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char log[LOG_BUFFER_LENGTH];
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va_list args;
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if ((log_mask & g->log_mask) == 0) {
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return;
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}
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va_start(args, fmt);
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(void) vsnprintf(log, LOG_BUFFER_LENGTH, fmt, args);
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va_end(args);
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__nvgpu_really_print_log(nvgpu_log_name(g),
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func_name, line, NVGPU_DEBUG, log);
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}
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