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MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed by brackets. This patch adds brackets to single line if/else/loop blocks in the POSIX code. JIRA NVGPU-775 Change-Id: Idafd5a5068c23b850ad1b0b083550a75b35588c1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2011739 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
278 lines
6.8 KiB
C
278 lines
6.8 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/nvgpu_sgt.h>
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#include <nvgpu/nvgpu_sgt_os.h>
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#include <nvgpu/gk20a.h>
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#include <os/posix/os_posix.h>
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#define DMA_ERROR_CODE (~(u64)0x0)
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/*
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* These functions are somewhat meaningless.
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*/
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u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem)
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{
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return (u64)(uintptr_t)mem->cpu_va;
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}
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u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem)
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{
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return (u64)(uintptr_t)mem->cpu_va;
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}
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struct nvgpu_sgl *nvgpu_mem_sgl_next(struct nvgpu_sgl *sgl)
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{
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struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl;
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return (struct nvgpu_sgl *) mem->next;
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}
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u64 nvgpu_mem_sgl_phys(struct gk20a *g, struct nvgpu_sgl *sgl)
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{
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struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl;
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return (u64)(uintptr_t)mem->phys;
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}
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u64 nvgpu_mem_sgl_ipa_to_pa(struct gk20a *g, struct nvgpu_sgl *sgl,
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u64 ipa, u64 *pa_len)
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{
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return nvgpu_mem_sgl_phys(g, sgl);
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}
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u64 nvgpu_mem_sgl_dma(struct nvgpu_sgl *sgl)
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{
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struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl;
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return (u64)(uintptr_t)mem->dma;
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}
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u64 nvgpu_mem_sgl_length(struct nvgpu_sgl *sgl)
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{
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struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl;
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return (u64)mem->length;
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}
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u64 nvgpu_mem_sgl_gpu_addr(struct gk20a *g, struct nvgpu_sgl *sgl,
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struct nvgpu_gmmu_attrs *attrs)
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{
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struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl;
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if (mem->dma == 0U) {
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return g->ops.mm.gpu_phys_addr(g, attrs, mem->phys);
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}
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if (mem->dma == DMA_ERROR_CODE) {
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return 0x0;
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}
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return nvgpu_mem_iommu_translate(g, mem->dma);
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}
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bool nvgpu_mem_sgt_iommuable(struct gk20a *g, struct nvgpu_sgt *sgt)
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{
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struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
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return p->mm_sgt_is_iommuable;
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}
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void nvgpu_mem_sgl_free(struct gk20a *g, struct nvgpu_mem_sgl *sgl)
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{
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struct nvgpu_mem_sgl *tptr;
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while (sgl != NULL) {
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tptr = sgl->next;
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nvgpu_kfree(g, sgl);
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sgl = tptr;
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}
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}
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void nvgpu_mem_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt)
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{
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nvgpu_mem_sgl_free(g, (struct nvgpu_mem_sgl *)sgt->sgl);
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nvgpu_kfree(g, sgt);
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}
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static struct nvgpu_sgt_ops nvgpu_sgt_posix_ops = {
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.sgl_next = nvgpu_mem_sgl_next,
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.sgl_phys = nvgpu_mem_sgl_phys,
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.sgl_ipa = nvgpu_mem_sgl_phys,
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.sgl_ipa_to_pa = nvgpu_mem_sgl_ipa_to_pa,
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.sgl_dma = nvgpu_mem_sgl_dma,
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.sgl_length = nvgpu_mem_sgl_length,
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.sgl_gpu_addr = nvgpu_mem_sgl_gpu_addr,
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.sgt_iommuable = nvgpu_mem_sgt_iommuable,
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.sgt_free = nvgpu_mem_sgt_free,
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};
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struct nvgpu_mem_sgl *nvgpu_mem_sgl_posix_create_from_list(struct gk20a *g,
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struct nvgpu_mem_sgl *sgl_list, u32 nr_sgls,
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u64 *total_size)
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{
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struct nvgpu_mem_sgl *sgl_ptr, *tptr, *head = NULL;
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u32 i;
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*total_size = 0;
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for (i = 0; i < nr_sgls; i++) {
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tptr = (struct nvgpu_mem_sgl *)nvgpu_kzalloc(g,
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sizeof(struct nvgpu_mem_sgl));
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if (tptr == NULL) {
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return NULL;
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}
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if (i == 0U) {
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sgl_ptr = tptr;
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head = sgl_ptr;
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} else {
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sgl_ptr->next = tptr;
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sgl_ptr = sgl_ptr->next;
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}
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sgl_ptr->next = NULL;
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sgl_ptr->phys = sgl_list[i].phys;
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sgl_ptr->dma = sgl_list[i].dma;
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sgl_ptr->length = sgl_list[i].length;
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*total_size += sgl_list[i].length;
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}
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return head;
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}
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struct nvgpu_sgt *nvgpu_mem_sgt_posix_create_from_list(struct gk20a *g,
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struct nvgpu_mem_sgl *sgl_list, u32 nr_sgls,
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u64 *total_size)
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{
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struct nvgpu_sgt *sgt = nvgpu_kzalloc(g, sizeof(struct nvgpu_sgt));
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struct nvgpu_mem_sgl *sgl;
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if (sgt == NULL) {
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return NULL;
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}
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sgl = nvgpu_mem_sgl_posix_create_from_list(g, sgl_list, nr_sgls,
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total_size);
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if (sgl == NULL) {
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nvgpu_kfree(g, sgt);
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return NULL;
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}
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sgt->sgl = (struct nvgpu_sgl *)sgl;
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sgt->ops = &nvgpu_sgt_posix_ops;
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return sgt;
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}
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int nvgpu_mem_posix_create_from_list(struct gk20a *g, struct nvgpu_mem *mem,
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struct nvgpu_mem_sgl *sgl_list, u32 nr_sgls)
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{
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u64 sgl_size;
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mem->priv.sgt = nvgpu_mem_sgt_posix_create_from_list(g, sgl_list,
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nr_sgls, &sgl_size);
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if (mem->priv.sgt == NULL) {
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return -ENOMEM;
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}
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mem->aperture = APERTURE_SYSMEM;
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mem->aligned_size = PAGE_ALIGN(sgl_size);
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mem->size = sgl_size;
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return 0;
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}
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struct nvgpu_sgt *nvgpu_sgt_os_create_from_mem(struct gk20a *g,
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struct nvgpu_mem *mem)
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{
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struct nvgpu_mem_sgl *sgl;
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struct nvgpu_sgt *sgt = nvgpu_kzalloc(g, sizeof(*sgt));
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if (sgt == NULL) {
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return NULL;
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}
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/*
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* The userspace implementation is simple: a single 'entry' (which we
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* only need the nvgpu_mem_sgl struct to describe). A unit test can
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* easily replace it if needed.
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*/
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sgt->ops = &nvgpu_sgt_posix_ops;
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if (mem->priv.sgt != NULL) {
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return mem->priv.sgt;
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} else {
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sgl = (struct nvgpu_mem_sgl *) nvgpu_kzalloc(g, sizeof(
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struct nvgpu_mem_sgl));
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if (sgl == NULL) {
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nvgpu_kfree(g, sgt);
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return NULL;
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}
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sgl->length = mem->size;
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sgl->phys = (u64) mem->cpu_va;
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sgt->sgl = (struct nvgpu_sgl *) sgl;
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}
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return sgt;
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}
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int nvgpu_mem_create_from_mem(struct gk20a *g,
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struct nvgpu_mem *dest, struct nvgpu_mem *src,
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u64 start_page, int nr_pages)
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{
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u64 start = start_page * U64(PAGE_SIZE);
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u64 size = U64(nr_pages) * U64(PAGE_SIZE);
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if (src->aperture != APERTURE_SYSMEM) {
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return -EINVAL;
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}
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/* Some silly things a caller might do... */
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if (size > src->size) {
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return -EINVAL;
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}
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if ((start + size) > src->size) {
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return -EINVAL;
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}
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(void) memset(dest, 0, sizeof(*dest));
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dest->cpu_va = ((char *)src->cpu_va) + start;
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dest->mem_flags = src->mem_flags | NVGPU_MEM_FLAG_SHADOW_COPY;
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dest->aperture = src->aperture;
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dest->skip_wmb = src->skip_wmb;
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dest->size = size;
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return 0;
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}
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int __nvgpu_mem_create_from_phys(struct gk20a *g, struct nvgpu_mem *dest,
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u64 src_phys, int nr_pages)
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{
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BUG();
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return 0;
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}
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