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MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed by brackets. This patch adds brackets to single line if/else/loop blocks in the POSIX code. JIRA NVGPU-775 Change-Id: Idafd5a5068c23b850ad1b0b083550a75b35588c1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2011739 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
175 lines
3.9 KiB
C
175 lines
3.9 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <sys/time.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/log.h>
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#include <nvgpu/timers.h>
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static s64 now(void)
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{
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return nvgpu_current_time_ms();
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}
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/*
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* Returns true if a > b;
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*/
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static bool time_after(s64 a, s64 b)
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{
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return a - b > 0;
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}
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int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout,
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u32 duration, unsigned long flags)
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{
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if ((flags & ~NVGPU_TIMER_FLAG_MASK) != 0U) {
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return -EINVAL;
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}
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(void) memset(timeout, 0, sizeof(*timeout));
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timeout->g = g;
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timeout->flags = flags;
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if ((flags & NVGPU_TIMER_RETRY_TIMER) != 0U) {
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timeout->retries.max = duration;
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} else {
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timeout->time = nvgpu_current_time_ms() + (s64)duration;
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}
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return 0;
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}
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static int __nvgpu_timeout_expired_msg_cpu(struct nvgpu_timeout *timeout,
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void *caller,
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const char *fmt, va_list args)
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{
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struct gk20a *g = timeout->g;
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if (time_after(now(), timeout->time)) {
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if (!(timeout->flags & NVGPU_TIMER_SILENT_TIMEOUT)) {
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char buf[128];
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(void) vsnprintf(buf, sizeof(buf), fmt, args);
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nvgpu_err(g, "Timeout detected @ %p %s", caller, buf);
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}
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int __nvgpu_timeout_expired_msg_retry(struct nvgpu_timeout *timeout,
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void *caller,
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const char *fmt, va_list args)
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{
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struct gk20a *g = timeout->g;
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if (timeout->retries.attempted >= timeout->retries.max) {
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if (!(timeout->flags & NVGPU_TIMER_SILENT_TIMEOUT)) {
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char buf[128];
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(void) vsnprintf(buf, sizeof(buf), fmt, args);
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nvgpu_err(g, "No more retries @ %p %s", caller, buf);
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}
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return -ETIMEDOUT;
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}
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timeout->retries.attempted++;
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return 0;
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}
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int __nvgpu_timeout_expired_msg(struct nvgpu_timeout *timeout,
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void *caller, const char *fmt, ...)
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{
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int ret;
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va_list args;
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va_start(args, fmt);
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if ((timeout->flags & NVGPU_TIMER_RETRY_TIMER) != 0U) {
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ret = __nvgpu_timeout_expired_msg_retry(timeout, caller, fmt,
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args);
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} else {
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ret = __nvgpu_timeout_expired_msg_cpu(timeout, caller, fmt,
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args);
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}
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va_end(args);
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return ret;
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}
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int nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout)
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{
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if ((timeout->flags & NVGPU_TIMER_RETRY_TIMER) != 0U) {
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return timeout->retries.attempted >= timeout->retries.max;
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} else {
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return time_after(now(), timeout->time);
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}
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}
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void nvgpu_udelay(unsigned int usecs)
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{
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BUG();
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}
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void nvgpu_usleep_range(unsigned int min_us, unsigned int max_us)
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{
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BUG();
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}
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void nvgpu_msleep(unsigned int msecs)
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{
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BUG();
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}
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static inline s64 __nvgpu_current_time_us(void)
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{
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struct timeval now;
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s64 time_now;
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int ret;
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ret = gettimeofday(&now, NULL);
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if (ret != 0) {
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BUG();
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}
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time_now = ((s64)now.tv_sec * (s64)1000000) + (s64)now.tv_usec;
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return time_now;
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}
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s64 nvgpu_current_time_ms(void)
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{
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return __nvgpu_current_time_us() / (s64)1000;
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}
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u64 nvgpu_hr_timestamp(void)
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{
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return __nvgpu_current_time_us();
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}
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