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git://nv-tegra.nvidia.com/linux-nvgpu.git
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a5eb150635
Add new unit gr/config to initialize GR configuration like GPC/TPC count, MAX count and mask Create new structure nvgpu_gr_config that stores all the configuration and that is owned by the new unit Move below fields from struct gr_gk20a to nvgpu_gr_config in gr/config.h Struct gr_gk20a now only holds the pointer to struct nvgpu_gr_config u32 max_gpc_count; u32 max_tpc_per_gpc_count; u32 max_zcull_per_gpc_count; u32 max_tpc_count; u32 gpc_count; u32 tpc_count; u32 ppc_count; u32 zcb_count; u32 pe_count_per_gpc; u32 *gpc_tpc_count; u32 *gpc_ppc_count; u32 *gpc_zcb_count; u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC]; u32 *gpc_tpc_mask; u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC]; u32 *gpc_skip_mask; u8 *map_tiles; u32 map_tile_count; u32 map_row_offset; Remove gr->sys_count since it was already no longer used common/gr/config/gr_config.c unit now exposes the APIs to initialize the configuration and also to query the configuration values nvgpu_gr_config_init() is called to initialize GR configuration from gr_gk20a_init_gr_config() and gr_gk20a_init_map_tiles() is simply renamed as nvgpu_gr_config_init_map_tiles() Expose new API nvgpu_gr_config_deinit() to deinit the configuration Expose nvgpu_gr_config_get_*() APIs to query above configuration fields stored in nvgpu_gr_config structure Update vgpu_gr_init_gr_config() to initialize the configuration from gr->config structure Chip specific HALs that access GR register for initialization are implemented in common/gr/config/gr_config_gm20b.c Set these HALs for all GPUs Jira NVGPU-1879 Change-Id: Ided658b43124ea61b9f273b82b73fdde4ed3c8f0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012167 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
76 lines
3.2 KiB
C
76 lines
3.2 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_VGPU_H
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#define NVGPU_GR_VGPU_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct channel_gk20a;
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struct gr_gk20a;
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struct gr_zcull_info;
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struct zbc_entry;
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struct zbc_query_params;
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struct dbg_session_gk20a;
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struct tsg_gk20a;
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void vgpu_gr_detect_sm_arch(struct gk20a *g);
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void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg);
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void vgpu_gr_free_tsg_ctx(struct tsg_gk20a *tsg);
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int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags);
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int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
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struct channel_gk20a *c, u64 zcull_va,
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u32 mode);
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int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
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struct gr_zcull_info *zcull_params);
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u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config,
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u32 gpc_index);
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u32 vgpu_gr_get_max_fbps_count(struct gk20a *g);
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u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g);
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u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g);
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u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g);
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u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g);
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int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_entry *zbc_val);
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int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_query_params *query_params);
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int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
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struct channel_gk20a *ch, u64 sms, bool enable);
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int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
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struct channel_gk20a *ch, bool enable);
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int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
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struct channel_gk20a *ch, u64 gpu_va, u32 mode);
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int vgpu_gr_clear_sm_error_state(struct gk20a *g,
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struct channel_gk20a *ch, u32 sm_id);
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int vgpu_gr_suspend_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_resume_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
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int vgpu_gr_init_sm_id_table(struct gk20a *g);
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int vgpu_gr_init_fs_state(struct gk20a *g);
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int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable);
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#endif /* NVGPU_GR_VGPU_H */
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