mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 10:34:43 +03:00
c330d8fd98
Split out ops that belong to channel unit to a new section called channel. Channel is a broad concept; this includes just the code that accesses channel registers (ccsr_*). This is effectively just renaming; the implementation still stays put. The word "channel" is also dropped from certain HAL entries to avoid redundancy (e.g., channel.disable_channel -> channel.disable). fifo.get_num_fifos gets an entirely new name: channel.count. Jira NVGPU-1307 Change-Id: I9a08103e461bf3ddb743aa37ababee3e0c73c861 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017261 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
/*
|
|
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/vgpu/tegra_vgpu.h>
|
|
#include <nvgpu/vgpu/vgpu.h>
|
|
#include <nvgpu/gk20a.h>
|
|
#include <nvgpu/channel.h>
|
|
|
|
#include "vgpu_tsg_gv11b.h"
|
|
|
|
int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
|
|
struct channel_gk20a *ch)
|
|
{
|
|
struct tegra_vgpu_cmd_msg msg = {};
|
|
struct tegra_vgpu_tsg_bind_channel_ex_params *p =
|
|
&msg.params.tsg_bind_channel_ex;
|
|
int err;
|
|
struct gk20a *g = tsg->g;
|
|
|
|
nvgpu_log_fn(g, " ");
|
|
|
|
err = gk20a_tsg_bind_channel(tsg, ch);
|
|
if (err) {
|
|
return err;
|
|
}
|
|
|
|
msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX;
|
|
msg.handle = vgpu_get_handle(tsg->g);
|
|
p->tsg_id = tsg->tsgid;
|
|
p->ch_handle = ch->virt_ctx;
|
|
p->subctx_id = ch->subctx_id;
|
|
p->runqueue_sel = ch->runqueue_sel;
|
|
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
|
|
err = err ? err : msg.ret;
|
|
if (err) {
|
|
nvgpu_err(tsg->g,
|
|
"vgpu_gv11b_tsg_bind_channel failed, ch %d tsgid %d",
|
|
ch->chid, tsg->tsgid);
|
|
gk20a_tsg_unbind_channel(ch);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
int vgpu_gv11b_enable_tsg(struct tsg_gk20a *tsg)
|
|
{
|
|
struct gk20a *g = tsg->g;
|
|
struct channel_gk20a *ch;
|
|
struct channel_gk20a *last_ch = NULL;
|
|
|
|
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
|
|
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
|
|
g->ops.channel.enable(ch);
|
|
last_ch = ch;
|
|
}
|
|
nvgpu_rwsem_up_read(&tsg->ch_list_lock);
|
|
|
|
if (last_ch) {
|
|
g->ops.fifo.ring_channel_doorbell(last_ch);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|