mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
0dcf0ede81
- Clock arbiter has lot of linux dependent code so moved clk_arb.c to common/linux folder & clk_arb.h to include/nvgpu/clk_arb.h, this move helps to unblock QNX. - QNX must implement functions present under clk_arb.h as needed. JIRA NVGPU-33 Change-Id: I38369fafda9c2cb9ba2175b3e530e40d0c746601 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582473 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gk20a/gk20a.h"
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#include "clk_arb_gp106.h"
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u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
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{
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(void)g;
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return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK);
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}
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int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
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u16 *min_mhz, u16 *max_mhz)
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{
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enum nv_pmu_clk_clkwhich clkwhich;
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struct clk_set_info *p0_info;
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struct clk_set_info *p5_info;
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struct avfsfllobjs *pfllobjs = &(g->clk_pmu.avfs_fllobjs);
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u16 limit_min_mhz;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_MCLK:
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clkwhich = clkwhich_mclk;
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break;
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case CTRL_CLK_DOMAIN_GPC2CLK:
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clkwhich = clkwhich_gpc2clk;
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break;
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default:
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return -EINVAL;
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}
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p5_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P5, clkwhich);
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if (!p5_info)
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return -EINVAL;
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p0_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P0, clkwhich);
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if (!p0_info)
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return -EINVAL;
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limit_min_mhz = p5_info->min_mhz;
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/* WAR for DVCO min */
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if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK)
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if ((pfllobjs->max_min_freq_mhz) &&
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(pfllobjs->max_min_freq_mhz > limit_min_mhz))
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limit_min_mhz = pfllobjs->max_min_freq_mhz;
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*min_mhz = limit_min_mhz;
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*max_mhz = p0_info->max_mhz;
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return 0;
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}
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int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
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u16 *default_mhz)
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{
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enum nv_pmu_clk_clkwhich clkwhich;
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struct clk_set_info *p0_info;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_MCLK:
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clkwhich = clkwhich_mclk;
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break;
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case CTRL_CLK_DOMAIN_GPC2CLK:
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clkwhich = clkwhich_gpc2clk;
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break;
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default:
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return -EINVAL;
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}
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p0_info = pstate_get_clk_set_info(g,
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CTRL_PERF_PSTATE_P0, clkwhich);
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if (!p0_info)
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return -EINVAL;
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*default_mhz = p0_info->max_mhz;
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return 0;
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}
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