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830d3f10ca
With recent rework in nvgpu most of the <uapi/linux/nvgpu.h> includes are not needed so remove them Remove use of NVGPU_DBG_GPU_REG_OP_* in gk20a/gr_gk20a.c and use common definition instead Remove use of NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE in gp10b/fifo_gp10b.c by defining new common flag NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE and then parsing it in API nvgpu_gpfifo_user_flags_to_common_flags() Jira NVGPU-363 Change-Id: I8e653275ea3f443f24be7284d54f2115636aba3f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1606108 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
98 lines
3.0 KiB
C
98 lines
3.0 KiB
C
/*
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* Tegra GV11B GPU Debugger/Profiler Driver
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*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include "gk20a/gk20a.h"
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#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
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int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size)
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{
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struct mm_gk20a *mm = &g->mm;
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u32 virt_addr_lo;
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u32 virt_addr_hi;
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u32 inst_pa_page;
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int err;
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
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err = gk20a_busy(g);
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if (err) {
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nvgpu_err(g, "failed to poweron");
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return err;
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}
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err = gk20a_alloc_inst_block(g, &mm->perfbuf.inst_block);
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if (err)
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return err;
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g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0);
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virt_addr_lo = u64_lo32(offset);
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virt_addr_hi = u64_hi32(offset);
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gk20a_writel(g, perf_pmasys_outbase_r(), virt_addr_lo);
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gk20a_writel(g, perf_pmasys_outbaseupper_r(),
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perf_pmasys_outbaseupper_ptr_f(virt_addr_hi));
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gk20a_writel(g, perf_pmasys_outsize_r(), size);
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/* this field is aligned to 4K */
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inst_pa_page = nvgpu_inst_block_addr(g, &mm->perfbuf.inst_block) >> 12;
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gk20a_writel(g, perf_pmasys_mem_block_r(),
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perf_pmasys_mem_block_base_f(inst_pa_page) |
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perf_pmasys_mem_block_valid_true_f() |
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nvgpu_aperture_mask(g, &mm->perfbuf.inst_block,
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+ perf_pmasys_mem_block_target_sys_ncoh_f(),
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+ perf_pmasys_mem_block_target_lfb_f()));
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gk20a_idle(g);
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return 0;
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}
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/* must be called with dbg_sessions_lock held */
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int gv11b_perfbuf_disable_locked(struct gk20a *g)
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{
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int err;
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
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err = gk20a_busy(g);
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if (err) {
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nvgpu_err(g, "failed to poweron");
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return err;
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}
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gk20a_writel(g, perf_pmasys_outbase_r(), 0);
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gk20a_writel(g, perf_pmasys_outbaseupper_r(),
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perf_pmasys_outbaseupper_ptr_f(0));
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gk20a_writel(g, perf_pmasys_outsize_r(), 0);
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gk20a_writel(g, perf_pmasys_mem_block_r(),
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perf_pmasys_mem_block_base_f(0) |
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perf_pmasys_mem_block_valid_false_f() |
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perf_pmasys_mem_block_target_f(0));
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gk20a_idle(g);
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return 0;
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}
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