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Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist, and optionally check host and FECS status to preempt pending load of context not belonging to the calling channel on GR engine during context switch. This should be called immediately after a submit to decrease worst case submit to start latency for high interleave channel. There is less than 0.002% chance that the ioctl blocks up to couple miliseconds due to race condition of FECS status changing while being read. For GV11B it will always preempt pending load of unwanted context since there is no chance that ioctl blocks due to race condition. Also fix bug with host reschedule for multiple runlists which needs to write both runlist registers. Bug 1987640 Bug 1924808 Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
163 lines
4.9 KiB
C
163 lines
4.9 KiB
C
/*
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* GV11B Graphics
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/enabled.h>
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#include "gk20a/gk20a.h"
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#include "gp10b/gp10b.h"
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#include "gv11b/gv11b.h"
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#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
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void gv11b_detect_ecc_enabled_units(struct gk20a *g)
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{
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u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
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u32 opt_feature_fuses_override_disable =
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gk20a_readl(g,
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fuse_opt_feature_fuses_override_disable_r());
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u32 fecs_feature_override_ecc =
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gk20a_readl(g,
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gr_fecs_feature_override_ecc_r());
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if (opt_feature_fuses_override_disable) {
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if (opt_ecc_en) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_LRF, true);
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_DATA, true);
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_TAG, true);
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_ICACHE, true);
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__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
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__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
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}
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} else {
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/* SM LRF */
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if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
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fecs_feature_override_ecc)) {
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if (gr_fecs_feature_override_ecc_sm_lrf_v(
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fecs_feature_override_ecc)) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_LRF, true);
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}
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} else {
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if (opt_ecc_en) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_LRF, true);
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}
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}
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/* SM L1 DATA*/
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if (gr_fecs_feature_override_ecc_sm_l1_data_override_v(
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fecs_feature_override_ecc)) {
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if (gr_fecs_feature_override_ecc_sm_l1_data_v(
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fecs_feature_override_ecc)) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_DATA, true);
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}
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} else {
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if (opt_ecc_en) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_DATA, true);
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}
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}
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/* SM L1 TAG*/
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if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v(
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fecs_feature_override_ecc)) {
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if (gr_fecs_feature_override_ecc_sm_l1_tag_v(
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fecs_feature_override_ecc)) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_TAG, true);
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}
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} else {
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if (opt_ecc_en) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_TAG, true);
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}
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}
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/* SM ICACHE*/
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if (gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(
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fecs_feature_override_ecc) &&
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gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(
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fecs_feature_override_ecc)) {
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if (gr_fecs_feature_override_ecc_1_sm_l0_icache_v(
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fecs_feature_override_ecc) &&
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gr_fecs_feature_override_ecc_1_sm_l1_icache_v(
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fecs_feature_override_ecc)) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_ICACHE, true);
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}
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} else {
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if (opt_ecc_en) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_ICACHE, true);
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}
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}
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/* LTC */
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if (gr_fecs_feature_override_ecc_ltc_override_v(
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fecs_feature_override_ecc)) {
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if (gr_fecs_feature_override_ecc_ltc_v(
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fecs_feature_override_ecc)) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_LTC, true);
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}
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} else {
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if (opt_ecc_en) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_LTC, true);
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}
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}
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/* SM CBU */
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if (gr_fecs_feature_override_ecc_sm_cbu_override_v(
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fecs_feature_override_ecc)) {
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if (gr_fecs_feature_override_ecc_sm_cbu_v(
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fecs_feature_override_ecc)) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_CBU, true);
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}
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} else {
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if (opt_ecc_en) {
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__nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_CBU, true);
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}
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}
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}
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}
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int gv11b_init_gpu_characteristics(struct gk20a *g)
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{
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gk20a_init_gpu_characteristics(g);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
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return 0;
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}
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