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01e61860fa
Register gpcclk with Common Clock Framework to expose GPCPLL frequency control Bug 200233943 Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1236979 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
31 lines
1001 B
C
31 lines
1001 B
C
/*
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* GM20B Graphics
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _NVHOST_CLK_GM20B_H_
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#define _NVHOST_CLK_GM20B_H_
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#include <linux/mutex.h>
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void gm20b_init_clk_ops(struct gpu_ops *gops);
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#ifdef CONFIG_COMMON_CLK
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int gm20b_register_gpcclk(struct gk20a *g);
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#endif
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#endif /* _NVHOST_CLK_GM20B_H_ */
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