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cc4208a278
- Define fuse macros depending on kernel version as fuse offset got changed in K4.4 and for K4.4 fuse defines are defined in common header file (tegra-fuse.h) - Use fuse control read/write APIs when reading control registers for K4.4. Bug 200243956 Change-Id: I5a86ef58d9de17a273aea8d3ce8ad5772444dac2 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245824 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/*
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* GM20B GPC MMU
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*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVHOST_GM20B_GR_MMU_H
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#define _NVHOST_GM20B_GR_MMU_H
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#include <linux/version.h>
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struct gk20a;
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enum {
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MAXWELL_B = 0xB197,
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MAXWELL_COMPUTE_B = 0xB1C0,
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KEPLER_INLINE_TO_MEMORY_B= 0xA140,
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MAXWELL_DMA_COPY_A = 0xB0B5,
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MAXWELL_CHANNEL_GPFIFO_A= 0xB06F,
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};
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#define tegra_clk_writel(value, offset) \
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writel(value, IO_ADDRESS(0x60006000 + offset))
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0 0x48
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE BIT(28)
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
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#define FUSE_FUSEBYPASS_0 0x24
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#define FUSE_WRITE_ACCESS_SW_0 0x30
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#define FUSE_OPT_GPU_TPC0_DISABLE_0 0x30C
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#define FUSE_OPT_GPU_TPC1_DISABLE_0 0x33C
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#endif
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#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
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#define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280
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#define NVB197_SET_SHADER_EXCEPTIONS 0x1528
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#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528
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#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
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void gm20b_init_gr(struct gpu_ops *gops);
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void gr_gm20b_commit_global_attrib_cb(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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u64 addr, bool patch);
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int gr_gm20b_init_fs_state(struct gk20a *g);
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int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask);
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#endif
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