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1040a3a534
Use an enum instead of an int as a return type for this function. This resolves violations of MISRA 10.3 that prohibits implicit assignment between types. JIRA NVGPU-647 Change-Id: I2a3725b28c6db9c1540da25228df3da184dd2e6d Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1917632 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
50 lines
2.1 KiB
C
50 lines
2.1 KiB
C
/*
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* GP10B Fifo
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_GP10B_H
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#define FIFO_GP10B_H
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struct gpu_ops;
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struct channel_gk20a;
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struct fifo_gk20a;
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struct mmu_fault_info;
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int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
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u64 gpfifo_base, u32 gpfifo_entries,
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unsigned long acquire_timeout, u32 flags);
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u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g);
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int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c);
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enum fifo_engine gp10b_fifo_engine_enum_from_type(struct gk20a *g,
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u32 engine_type, u32 *inst_id);
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void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
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u32 *inst_id, u32 *pri_base, u32 *fault_id);
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void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
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void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
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struct mmu_fault_info *mmfault);
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void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault);
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void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault);
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int channel_gp10b_commit_userd(struct channel_gk20a *c);
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#endif
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