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git://nv-tegra.nvidia.com/linux-nvgpu.git
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bcbc87dc2e
Interface header files for PMU features are now moved under PMU header files directory include/nvgpu/pmu. And fix bulk of coding style issues. Update header file names and guards. JIRA NVGPU-1971 Change-Id: Idf53fc09d8928d1b0a1cd16eef886de010dae06b Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093006 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
88 lines
2.8 KiB
C
88 lines
2.8 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/boardobj.h>
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#include <nvgpu/boardobjgrp.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/boardobjgrpmask.h>
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#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
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int boardobjgrpconstruct_e32(struct gk20a *g,
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struct boardobjgrp_e32 *pboardobjgrp_e32)
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{
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int status;
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u8 objslots;
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nvgpu_log_info(g, " ");
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objslots = 32;
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status = boardobjgrpmask_e32_init(&pboardobjgrp_e32->mask, NULL);
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if (status != 0) {
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goto boardobjgrpconstruct_e32_exit;
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}
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pboardobjgrp_e32->super.type = CTRL_BOARDOBJGRP_TYPE_E32;
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pboardobjgrp_e32->super.ppobjects = pboardobjgrp_e32->objects;
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pboardobjgrp_e32->super.objslots = objslots;
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pboardobjgrp_e32->super.mask = &(pboardobjgrp_e32->mask.super);
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status = boardobjgrp_construct_super(g, &pboardobjgrp_e32->super);
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if (status != 0) {
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goto boardobjgrpconstruct_e32_exit;
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}
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pboardobjgrp_e32->super.pmuhdrdatainit = boardobjgrp_pmuhdrdatainit_e32;
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boardobjgrpconstruct_e32_exit:
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return status;
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}
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int boardobjgrp_pmuhdrdatainit_e32(struct gk20a *g,
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struct boardobjgrp *pboardobjgrp,
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struct nv_pmu_boardobjgrp_super *pboardobjgrppmu,
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struct boardobjgrpmask *mask)
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{
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struct nv_pmu_boardobjgrp_e32 *pgrpe32 =
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(struct nv_pmu_boardobjgrp_e32 *)pboardobjgrppmu;
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int status;
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nvgpu_log_info(g, " ");
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if (pboardobjgrp == NULL) {
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return -EINVAL;
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}
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if (pboardobjgrppmu == NULL) {
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return -EINVAL;
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}
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status = boardobjgrpmask_export(mask,
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mask->bitcount,
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&pgrpe32->obj_mask.super);
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if (status != 0) {
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nvgpu_err(g, "e32 init:failed export grpmask");
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return status;
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}
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return boardobjgrp_pmuhdrdatainit_super(g,
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pboardobjgrp, pboardobjgrppmu, mask);
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}
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