mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 01:50:07 +03:00
1160f083d4
Merged gk20a_ce_delete_context and gk20a_ce_delete_context_priv. Renamed - gk20a_init_ce_support -> nvgpu_ce_init_support - gk20a_ce_destroy -> nvgpu_ce_destroy - gk20a_ce_suspend -> nvgpu_ce_suspend - gk20a_ce_create_context -> nvgpu_ce_create_context - gk20a_ce_delete_context -> nvgpu_ce_delete_context - gk20a_ce_execute_ops -> nvgpu_ce_execute_ops - gk20a_ce_prepare_submit -> nvgpu_ce_prepare_submit - gk20a_ce_put_fences -> nvgpu_ce_put_fences - gk20a_ce_delete_gpu_context -> nvgpu_ce_delete_gpu_context - gk20a_ce_get_method_size -> nvgpu_ce_get_method_size - gk20a_gpu_ctx -> nvgpu_ce_gpu_ctx - gk20a_gpu_ctx_from_list -> nvgpu_ce_gpu_ctx_from_list - gk20a_ce_app -> nvgpu_ce_app - gk20a_ce_debugfs_init -> nvgpu_ce_debugfs_init - gk20a_get_valid_launch_flags -> nvgpu_ce_get_valid_launch_flags - gk20a_ce2_isr -> gk20a_ce2_stall_isr - gp10b_ce_isr -> gp10b_ce_stall_isr - gv11b_ce_isr -> gv11b_ce_stall_isr Inlined - ce*_nonblockpipe_isr - ce*_blockpipe_isr - ce*_launcherr_isr Added ce_priv.h for ce private definitions. Moved files to common/ce and hal/fifo/ce - ce2.c -> common/ce2/ce.c - ce2_gk20a.c -> hal/ce/ce2_gk20a.c - ce2_gk20a.h -> hal/ce/ce2_gk20a.h - ce_gp10b.c -> hal/ce/ce_gp10b.c - ce_gp10b.h -> hal/ce/ce_gp10b.h - ce_gv11b.c -> hal/ce/ce_gv11b.c - ce_gv11b.h -> hal/ce/ce_gv11b.h Updated makefiles and #include directives Jira NVGPU-1992 Change-Id: Ia6064bf51b7a254085be43a112d056cb6fb6c3b2 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093503 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CE_PRIV_H
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#define NVGPU_CE_PRIV_H
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#include <nvgpu/types.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/list.h>
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#include <nvgpu/lock.h>
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/*
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* Copy engine defines line size in pixels
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*/
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#define MAX_CE_SHIFT 31U /* 4Gpixels -1 */
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#define MAX_CE_MASK ((u32) (~(~0U << MAX_CE_SHIFT)))
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#define MAX_CE_ALIGN(a) ((a) & MAX_CE_MASK)
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struct gk20a;
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/* ce context db */
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struct nvgpu_ce_gpu_ctx {
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struct gk20a *g;
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u32 ctx_id;
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struct nvgpu_mutex gpu_ctx_mutex;
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int gpu_ctx_state;
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/* tsg related data */
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struct tsg_gk20a *tsg;
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/* channel related data */
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struct channel_gk20a *ch;
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struct vm_gk20a *vm;
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/* cmd buf mem_desc */
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struct nvgpu_mem cmd_buf_mem;
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struct nvgpu_fence_type *postfences[NVGPU_CE_MAX_INFLIGHT_JOBS];
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struct nvgpu_list_node list;
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u32 cmd_buf_read_queue_offset;
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};
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/* global ce app db */
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struct nvgpu_ce_app {
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bool initialised;
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struct nvgpu_mutex app_mutex;
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int app_state;
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struct nvgpu_list_node allocated_contexts;
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u32 ctx_count;
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u32 next_ctx_id;
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};
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static inline struct nvgpu_ce_gpu_ctx *
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nvgpu_ce_gpu_ctx_from_list(struct nvgpu_list_node *node)
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{
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return (struct nvgpu_ce_gpu_ctx *)
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((uintptr_t)node - offsetof(struct nvgpu_ce_gpu_ctx, list));
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};
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u32 nvgpu_ce_prepare_submit(u64 src_buf,
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u64 dst_buf,
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u64 size,
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u32 *cmd_buf_cpu_va,
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u32 max_cmd_buf_size,
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unsigned int payload,
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u32 launch_flags,
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u32 request_operation,
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u32 dma_copy_class);
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#endif /*NVGPU_CE_PRIV_H*/
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