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a91535e3a3
Basic units like fifo, rc are having dependency on gr_falcon. Avoided outside gr units dependency on gr_falcon by moving following functions to gr: int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g, struct nvgpu_gr_falcon *falcon); -> int nvgpu_gr_disable_ctxsw(struct gk20a *g); int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g, struct nvgpu_gr_falcon *falcon); -> int nvgpu_gr_enable_ctxsw(struct gk20a *g); int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); -> int nvgpu_gr_halt_pipe(struct gk20a *g); HALs also moved accordingly and updated code to reflect this. Also moved following data back to gr from gr_falcon: struct nvgpu_mutex ctxsw_disable_mutex; int ctxsw_disable_count; JIRA NVGPU-3168 Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2100009 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
45 lines
1.8 KiB
C
45 lines
1.8 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_H
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#define NVGPU_GR_H
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#include <nvgpu/types.h>
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int nvgpu_gr_prepare_sw(struct gk20a *g);
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int nvgpu_gr_enable_hw(struct gk20a *g);
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int nvgpu_gr_reset(struct gk20a *g);
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int nvgpu_gr_init_support(struct gk20a *g);
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u32 nvgpu_gr_gpc_offset(struct gk20a *g, u32 gpc);
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u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc);
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int nvgpu_gr_suspend(struct gk20a *g);
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void nvgpu_gr_flush_channel_tlb(struct gk20a *g);
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void nvgpu_gr_wait_initialized(struct gk20a *g);
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void nvgpu_gr_init(struct gk20a *g);
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int nvgpu_gr_alloc(struct gk20a *g);
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void nvgpu_gr_free(struct gk20a *g);
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int nvgpu_gr_disable_ctxsw(struct gk20a *g);
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int nvgpu_gr_enable_ctxsw(struct gk20a *g);
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int nvgpu_gr_halt_pipe(struct gk20a *g);
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#endif /* NVGPU_GR_H */
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