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e9b03e903c
Add sysfs nodes for querying ECC single/double bit error counts. Bug 1699676 Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935363 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
/*
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* GM20B GPU GR
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*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVGPU_GR_GP10B_H_
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#define _NVGPU_GR_GP10B_H_
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struct gpu_ops;
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enum {
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PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
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PASCAL_A = 0xC097,
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PASCAL_COMPUTE_A = 0xC0C0,
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PASCAL_DMA_COPY_A = 0xC0B5,
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};
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#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
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#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
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void gp10b_init_gr(struct gpu_ops *ops);
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int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
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struct mem_desc *mem);
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void gr_gp10b_create_sysfs(struct platform_device *dev);
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struct ecc_stat {
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char **names;
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u32 *counters;
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struct hlist_node hash_node;
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};
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struct gr_t18x {
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struct {
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u32 preempt_image_size;
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u32 force_preemption_gfxp;
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u32 force_preemption_cilp;
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u32 dump_ctxsw_stats_on_channel_close;
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struct dentry *debugfs_force_preemption_cilp;
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struct dentry *debugfs_force_preemption_gfxp;
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struct dentry *debugfs_dump_ctxsw_stats;
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} ctx_vars;
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struct {
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struct ecc_stat sm_lrf_single_err_count;
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struct ecc_stat sm_lrf_double_err_count;
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struct ecc_stat sm_shm_sec_count;
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struct ecc_stat sm_shm_sed_count;
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struct ecc_stat sm_shm_ded_count;
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struct ecc_stat tex_total_sec_pipe0_count;
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struct ecc_stat tex_total_ded_pipe0_count;
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struct ecc_stat tex_unique_sec_pipe0_count;
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struct ecc_stat tex_unique_ded_pipe0_count;
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struct ecc_stat tex_total_sec_pipe1_count;
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struct ecc_stat tex_total_ded_pipe1_count;
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struct ecc_stat tex_unique_sec_pipe1_count;
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struct ecc_stat tex_unique_ded_pipe1_count;
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struct ecc_stat l2_sec_count;
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struct ecc_stat l2_ded_count;
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} ecc_stats;
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int cilp_preempt_pending_chid;
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};
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struct gr_ctx_desc_t18x {
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struct mem_desc preempt_ctxsw_buffer;
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struct mem_desc spill_ctxsw_buffer;
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struct mem_desc betacb_ctxsw_buffer;
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struct mem_desc pagepool_ctxsw_buffer;
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u32 ctx_id;
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bool ctx_id_valid;
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bool cilp_preempt_pending;
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};
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#define NVGPU_GR_PREEMPTION_MODE_GFXP 1
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#define NVGPU_GR_PREEMPTION_MODE_CILP 3
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#endif
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