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66ed536fb5
Add defines and interface structures used for sending PMU messages to control RPPG. JIRA DNVGPU-71 Change-Id: Ibec975f3c976619542d8f088b24271796a03f03c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247487 (cherry picked from commit dd3826abca0a51d473d5d9cb25dc84cada9e7878) Reviewed-on: http://git-master/r/1270793 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
102 lines
2.0 KiB
C
102 lines
2.0 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GPMUIFRPPG_H_
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#define _GPMUIFRPPG_H_
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#define NV_PMU_RPPG_CTRL_ID_GR (0x0000)
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#define NV_PMU_RPPG_CTRL_ID_MS (0x0001)
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#define NV_PMU_RPPG_CTRL_ID_DI (0x0002)
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#define NV_PMU_RPPG_CTRL_ID_MAX (0x0003)
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#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\
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BIT(NV_PMU_RPPG_CTRL_ID_MS) |\
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BIT(NV_PMU_RPPG_CTRL_ID_DI))
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#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0
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enum {
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NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0,
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NV_PMU_RPPG_DOMAIN_ID_NON_GFX,
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};
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struct nv_pmu_rppg_ctrl_stats {
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u32 entry_count;
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u32 exit_count;
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};
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struct nv_pmu_rppg_cmd_common {
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u8 cmd_type;
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u8 cmd_id;
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};
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struct nv_pmu_rppg_cmd_init {
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u8 cmd_type;
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u8 cmd_id;
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};
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struct nv_pmu_rppg_cmd_init_ctrl {
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u8 cmd_type;
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u8 cmd_id;
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u8 ctrl_id;
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u8 domain_id;
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};
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struct nv_pmu_rppg_cmd_stats_reset {
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u8 cmd_type;
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u8 cmd_id;
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u8 ctrl_id;
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};
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struct nv_pmu_rppg_cmd {
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union {
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u8 cmd_type;
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struct nv_pmu_rppg_cmd_common cmn;
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struct nv_pmu_rppg_cmd_init init;
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struct nv_pmu_rppg_cmd_init_ctrl init_ctrl;
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struct nv_pmu_rppg_cmd_stats_reset stats_reset;
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};
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};
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enum {
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NV_PMU_RPPG_CMD_ID_INIT = 0x0,
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NV_PMU_RPPG_CMD_ID_INIT_CTRL,
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NV_PMU_RPPG_CMD_ID_STATS_RESET,
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};
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struct nv_pmu_rppg_msg_common {
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u8 msg_type;
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u8 msg_id;
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};
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struct nv_pmu_rppg_msg_init_ctrl_ack {
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u8 msg_type;
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u8 msg_id;
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u8 ctrl_id;
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u32 stats_dmem_offset;
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};
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struct nv_pmu_rppg_msg {
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union {
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u8 msg_type;
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struct nv_pmu_rppg_msg_common cmn;
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struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack;
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};
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};
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enum {
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NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0,
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};
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#endif
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